US 2002/0056027 A1 · Information processing system

Abstract

An information processing system which reduces an access latency from a memory read request of a processor to a response thereto and also prevents reduction of the effective performance of a system bus caused by an increase in the access latency. In the information processing system, a memory controller is connected with the processor via a first bus and connected with a memory via a second bus, and a buffer memory is provided in the memory controller. The control circuit is controlled, before a memory access from the processor is carried out, to estimate an address to be possibly next accessed on the basis of addresses accessed in the past and to prefetch into the buffer memory, data stored in an address area continuous to the address and having a data size of twice or more an access unit of the processor.

Claims16

Dependent claims

An information processing system comprising:

a processor;
a memory;
and
a memory controller connected with said processor via a first bus and connected with said memory via a second bus for controlling said memory,
wherein said memory controller comprises a buffer memory and a control circuit, and said control circuit is controlled, before a memory access is carried out from said processor, to estimate an address to be possibly next accessed on the basis of addresses accessed in the past and to prefetch data stored in said memory into said buffer memory, in accordance with said estimated address wherein said data has a data size of twice or more an access unit of said processor.

2 more elements

Dependencies are inferred from the claim text.

Information processing system

Life of this patent

Information processing system

Life of this patent

Abstract

Claims16