Method and device for controlling cache memory

A cache memory control method for reading an information requested by a processor from a cache memory or a main memory of a data processing device and supplying the information to said processor, said data processing device including tag memories for storing tags constituting addresses corresponding to information stored in said cache memory, a first buffer for temporarily storing a tag read out from said tag memories, a second buffer for temporarily storing an information read out from said main memory and a third buffer for temporarily storing an address of an information temporarily stored in said second buffer, said cache memory control method comprising:

• a first processing for reading the information from said cache memory or said second buffer and supplying the information to said processor when an address supplied from said processor and corresponding to the information requested by said processor or a tag constituting the address is coincident with an address temporarily stored in said third buffer or a tag temporarily stored in said first buffer, or reading the tag constituting the address supplied from said processor from said tag memories and temporarily storing the tag in said first buffer when the address supplied from said processor and corresponding to the information requested by said processor or the tag constituting the address is not coincident with the address temporarily stored in said third buffer or the tag temporarily stored in said first buffer;
• and
• a second processing for reading the information from said cache memory and supplying the information to said processor when the tag constituting the address supplied from said processor is coincident with the tag temporarily stored in said first buffer or reading the information from said main memory on the basis of the address supplied from said processor, temporarily storing the information in said second buffer and in said cache memory and temporarily storing addresses temporarily stored in said third and second buffers when the tag constituting the address supplied from said processor is not coincident with the tag temporarily stored in said first buffer.

A cache memory control method for reading an information requested by a processor from a cache memory or a main memory of a data processing device and supplying the information to said processor, said data processing device including tag memories for storing tags constituting addresses corresponding to information stored in said cache memory, a tag buffer for temporarily storing a tag read out from said tag memories, an information buffer for temporarily storing an information read out from said main memory, a backup buffer for temporarily storing an address of the information temporarily stored in said information buffer, a last buffer for temporarily storing a newest tag, a next buffer for temporarily storing a tag adjacent to the tag constituting the address supplied from said processor and corresponding to the information requested thereby and a branch buffer for temporarily storing a tag constituting an address of an information temporarily stored in a discontinuous memory region of said main memory when the information is requested by said processor, said cache memory control method comprising:

• a first processing for reading the information from said cache memory or said information buffer and supplying the information to said processor when an address supplied from said processor or a tag constituting the address is coincident with an address temporarily stored in said backup buffer or a tag temporarily stored in said last buffer, said next buffer or said branch buffer;
• a second processing for reading the information from said cache memory and supplying the information to said processor when the tag constituting the address supplied from said processor is coincident with the tag temporarily stored in said tag buffer;
• a third processing reading the information from said main memory on the basis of the address supplied from said processor, temporarily storing the information in said information buffer and in said cache memory and temporarily storing addresses of the information temporarily stored in said information buffer in said backup buffer;
• a fourth processing for reading the tag constituting the address supplied from said processor from said tag memories and temporarily storing the tag in said tag buffer;
• and
• a fifth processing for reading the tag adjacent to the tag constituting the address supplied from said processor and temporarily storing the adjacent tag in said next buffer, and, the information stored in said discontinuous memory region of said main memory is requested by said processor, temporarily storing the tag constituting the address corresponding to the information in said branch buffer and, otherwise, temporarily storing the information in said last buffer.

A cache memory control device for reading an information requested by a processor from a cache memory or a main memory of a data processing device and supplying the information to said processor, comprising:

• tag memories for storing tags constituting addresses corresponding to information stored in said cache memory;
• at least one buffer for reading a tag constituting an address corresponding to an information predicted as to be requested next by said processor, on a basis of an address supplied from said processor and corresponding to a requested information, and temporarily storing said tag in at least one of said tag memories;
• and
• a comparator for comparing said tag constituting the address supplied next by said processor with said tag temporarily stored in said buffer, before said tag constituting the address supplied next by said processor is read out from said at least one of said tag memories.

A cache memory control device for reading an information requested by a processor from a cache memory or a main memory of a data processing device and supplying the information to said processor, comprising:

• tag memories for storing tags constituting addresses corresponding to information stored in said cache memory;
• a first buffer for temporarily storing a tag read out from said tag memories;
• a second buffer for temporarily storing an information read out from said main memory;
• a third buffer for temporarily storing an address of an information temporarily stored in said second buffer;
• a first comparator for comparing a tag constituting an address supplied from said processor and corresponding to an information requested by said processor with a tag temporarily stored in said first buffer and outputting a hit signal when the tags are coincident;
• a second comparator for comparing the address supplied from said processor with the address temporarily stored in said third buffer and outputting a hit signal when the addresses are coincident, wherein the information is read out from said cache memory or said second buffer and supplied to said processor when either said first or second comparator outputs a hit signal, the tag constituting the address supplied from said processor is read out from said tag memory and temporarily stored in said first buffer when neither said first nor second comparator outputs a hit signal, the information read out from said cache memory and supplied to said processor when said first comparator outputs the hit signal, or the information is read out from said main memory on the basis of the address supplied from said processor and temporarily stored in said second buffer and said cache memory and the address of the information temporarily stored in said second buffer is temporarily stored in said third buffer when said first comparator outputs no hit signal.

A cache memory control device for reading an information requested by a processor from a cache memory or a main memory of a data processing device and supplying the information to said processor, comprising:

• tag memories for storing tags constituting addresses corresponding to information stored in said cache memory;
• a tag buffer for temporarily storing a tag read out from said tag memories;
• an information buffer for temporarily storing an information read out from said main memory;
• a backup buffer for temporarily storing an address of an information temporarily stored in said information buffer;
• a last buffer for temporarily storing a newest tag;
• a next buffer for temporarily storing a tag adjacent to the tag constituting an address supplied from said processor and corresponding to an information requested by said processor;
• a branch buffer for temporarily storing a tag constituting an address of an information temporarily stored in a discontinuous memory region of said main memory when the information is requested by said processor;
• a first, second, third and fourth comparators each for comparing a tag constituting an address supplied from said processor and corresponding to an information requested by said processor with a tag temporarily stored in different one of said tag buffer, said last buffer, said next buffer and said branch buffer and outputting a hit signal when the tags are coincident;
• and
• a fifth comparator for comparing the address supplied from said processor with the address temporarily stored in said backup buffer and outputting a hit signal when the addresses are coincident, wherein said cache memory control device takes in:
• a first state in which, when said second to fifth comparators output the hit signals, the information is read out from said cache memory or said information buffer and supplied to said processor;
• a second state in which, when said first comparator outputs the hit signal, the information is read out from said cache memory and supplied to said processor;
• a third state in which the information is read out from said main memory on the basis of the address supplied from said processor, temporarily storing the information in said information buffer and in said cache memory and addresses of the information temporarily stored in said information buffer are temporarily stored in said backup buffer;
• a fourth state in which the tag constituting the address supplied from said processor is read out from said tag memories and temporarily stored in said tag buffer;
• and
• a fifth state in which the tag adjacent to the tag constituting the address supplied from said processor is read out from said tag memories and temporarily stored in said next buffer, and, when the information stored in said discontinuous memory region of said main memory is requested by said processor, the tag constituting the address corresponding to the information is temporarily stored in said branch buffer and, otherwise, the tag constituting the address corresponding to the information is temporarily stored in said last buffer.