Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same

Abstract

A system for handling refresh of a DRAM array or other memory array requiring periodic refresh, such that the refresh does not require explicit control signaling between the memory array and a memory controller. External accesses and refresh operations are controlled so that the refresh operations do not interfere with the external accesses under any conditions. A multi-bank refresh scheme is used to reduce the number of collisions between external accesses and refresh operations. A read buffer buffers read data, thereby allowing refresh operations to be performed when consecutive read accesses hit the address range of the same memory bank for a long period of time. A write buffer buffers write data, thereby allowing refresh operations to be performed when consecutive write accesses hit the address range of a single memory bank for a long period of time. Both the read and write buffers can be constructed of DRAM cells.

Dependencies are inferred from the claim text.