Enhanced dram with embedded registers

An integrated circuit memory device comprising:

• a memory array;
• a cache integrated within and coupled for direct mapping by row address to said memory array;
• a column address latch coupled to said memory array;
• an address input coupled to said column address latch:
• a last row read address latch coupled to said cache and said address input;
• a comparator coupled to said last read row address latch and said address input;
• a row address latch coupled to said memory array and said address input;
• a refresh counter coupled to said memory array;
• an input and output control circuit coupled to said memory array and said cache;
• and
• an output coupled to said input and output control circuit.

An integrated circuit memory comprising:

• a plurality of connection pins;
• an integrated circuit connected to said connection pins, the integrated circuit including a plurality of DRAM memory cells arranged in an array, a plurality of row registers coupled selectively to said array, a coupling circuit connected between said array and said row registers and effective for selectively coupling and decoupling the array from the row registers, a row decoder coupled to said array, a refresh circuit coupled to said array, a column decoder, a plurality of sense amplifiers coupled to said array, and a plurality of output data buffers;
• wherein said plurality of pins includes:
• a plurality of address pins for receiving row and column addresses;
• a plurality of power supply pins for receiving power supply voltages;
• a plurality of data pins for receiving and outputting data bits;
• a chip select pin for receiving a chip select signal;
• a refresh control signal pin for receiving a refresh control signal;
• a write enable pin for receiving a write enable signal;
• a row enable pin for receiving a row enable signal;
• an output enable pin for receiving an output enable signal;
• a read/write control pin for receiving a read/write control signal;
• and
• a column address latch pin for receiving a column address latch signal.

A method of operating an integrated circuit memory having a DRAM portion, an on-chip cache portion coupled to the DRAM portion, and a plurality of connection pins, comprising the steps of:

• applying row and column addresses to a plurality of address pins;
• applying input data to a plurality of data pins in connection with a storing step where the input data is to be stored in the DRAM portion;
• receiving output data from said data pins representing data stored in the integrated circuit memory;
• applying a chip select signal to a chip select pin for enabling the on-chip cache portion to be activated so that data can be read therefrom without requiring access to the DRAM portion;
• and
• applying a row enable signal to a row enable pin to permit the DRAM portion to be accessed for writing to or reading from the DRAM portion.

A method of operating an integrated circuit memory having a DRAM portion, an on-chip cache portion coupled to the DRAM portion, and a plurality of connection pins, comprising the steps of:

• applying row and column addresses to a plurality of address pins;
• applying input data to a plurality of data pins in connection with a storing step where the input data is to be stored in the DRAM portion;
• receiving output data from said data pins representing data stored in the integrated circuit memory;
• applying a column address latch signal to a column address latch pin to control a column address latch in the integrated circuit memory;
• applying an output enable signal to an output enable pin to cause the integrated circuit memory to enable output circuits thereon;
• and
• determining on chip whether the integrated circuit memory will operate in static column mode or page mode on the basis of the state of said column address latch signal.

A method for data storage access comprising the steps of:

• reading from an integrated circuit cache memory in random access fashion;
• decoupling an integrated circuit memory array from said cache memory simultaneously with said reading step;
• and
• asynchronously operating said memory array contemporaneously with said reading step.