Phase locked loop including control circuit for reducing lock-time
AssigneeSamsung Electronics Co., Ltd.
InventorJong-Haeng Lee
Life of this patent
Estimating the term…
Abstract
A PLL circuit includes a control circuit for generating a reference control signal. A reception divider, reference divider, and transmission divider respectively divide an output signal of a receiver VCO according to a reception division data signal, an output signal of a crystal oscillator according to a reference division data signal, and an output signal of a transmitter VCO according to a transmission division data signal. A first and second phase detector respectively detect frequency and phase differences between a reception divider output and a reference divider output and between a transmission divider output and the reference divider output.
Claims16
A phase locked loop (PLL) circuit having a receiver voltage controlled oscillator (VCO), a transmitter VCO, and a crystal oscillator, the PLL circuit comprising:
- a control circuit for generating a reference control signal in response to a reception enable signal and a transmission enable signal;
- a reception divider for receiving a reception division data signal in response to the reception enable signal and dividing an output signal of the receiver VCO according to the reception division data signal;
- a reference divider for receiving a reference division data signal in response to the reference control signal of the control circuit and dividing the output signal of a crystal oscillator according to the reference division data signal;
- a transmission divider for receiving a transmission division data signal in response to the transmission enable signal and dividing an output signal of the transmitter VCO according to the transmission division data signal;
- a first phase detector for detecting frequency and phase differences between an output signal of the reception divider and an output signal of the reference divider;
- and
- a second phase detector for detecting the frequency and phase differences between an output signal of the transmission divider and the output signal of the reference divider.
A phase locked loop circuit h aving a receiver voltage controlled oscillator (VCO), a transmitter VCO, and a crystal oscillator, the PLL circuit comprising:
- a control circuit for outputting a reception control signal and a transmission control signal in response to a reception enable signal, and a transmission enable signal;
- a reception divider for receiving a reception division data signal in response to the reception control signal and dividing an output signal of the receiver VCO according to the reception division data signal;
- a reference divider for receiving a reference division data signal in response to a reference enable signal and dividing an output signal of the crystal oscillator according to the reference division data signal;
- a transmission divider for receiving a transmission division data signal in response to the transmission control signal of the control circuit and dividing an output signal of the transmitter VCO according to the transmission division data signal;
- a first phase detector for detecting frequency and phase differences between an output signal of the reception divider and an output of the reference divider;
- and
- a second phase detector for detecting the frequency and phase differences between an output signal of the transmission divider and an output signal of the reference divider.
Dependencies are inferred from the claim text.