Non-blocking, multi-context pipelined processor

A method for processing packets in a packet processor including a first logic block for performing one or more processing operations on packet data and a second logic block for performing one or more processing operations on packet data in response to packet data output from said first logic block, the method comprising the steps of:

• receiving by the first logic block at time T a first packet data;
• processing the first packet data;
• receiving by the first logic block at time T+t, wherein t>0, a second packet data;
• processing the second packet data;
• and
• outputting a third packet data to the second logic block in response to the second packet data input at time T+t prior to outputting a fourth packet data to the second logic block in response to the first packet data input at time T.

A method for processing packets in a packet processor including a first logic block operative for performing one or more processing operations on packet data and a second logic block for performing one or more processing operations on packet data in response to packet data output from said first logic block, the method comprising the steps of:

• receiving by the first logic block at time T a first packet data;
• outputting the first packet data to the second logic block;
• and
• receiving by the first logic block at time T+t, wherein t>0, a second packet data prior to outputting to the second logic block the first packet data received at time T.

A method for processing packets in a packet processor including a first logic block and a second logic block, the method comprising the steps of:

• receiving at the first logic block at time T a first packet data associated with a first packet;
• receiving at the first logic block at time T+t, wherein t>0, a second packet data associated with a second packet;
• alternating between processing the first packet data and the second packet data;
• and
• outputting to the second logic block the second packet data prior to outputting the first packet data.

A method for processing packets in a packet processor including a first logic block and a second logic block, the method comprising the steps of:

• receiving at the first logic block a first packet data associated with a first packet and;
• receiving at the first logic block a second packet data associated with a second packet;
• processing the first packet data;
• and
• switching from processing the first packet data to processing the second packet data while awaiting a processing result for the first packet data.

A method for processing packets in a pipelined processor having a plurality of logic blocks, the method comprising the steps of:

• performing at the first logic block a first operation on a first processing instruction associated with a first packet;
• forwarding the first processing instruction to a second logic block for performing a second operation;
• and
• receiving at the first logic block a second processing instruction associated with a second packet if a potential stall is expected in processing the first processing instruction, the first logic block performing the first operation on the second processing instruction concurrently with the second operation on the first processing instruction.