US 2002/0054537 A1 · Internal addressing structure of a semiconductor memory

Abstract

An internal addressing structure for a semiconductor memory with at least two memory banks, includes a counter associated for operation with each memory bank and capable of generating sequences of digital codes for addressing locations in the corresponding bank, a first circuit for causing a selective updating of the counters, a second circuit for loading into the counters a common initial digital code, forming part of an initial address supplied to the memory from the outside through an addressing line bus, corresponding to an initial memory location, and a third circuit capable of detecting a first signal, supplied to the memory from the outside and indicating the presence of a digital code on the bus, to cause the common initial digital code to be loaded into the counters. The first circuit means iscapable of identifying, on the basis of the initial address, the bank to which the initial memory location belongs, and of consequently causing the periodic updating of the counters in a sequence which depends on the bank to which the initial memory location belongs, in such a way that successive memory locations preceding or following the initial location are addressed in sequence, each of these successive locations belonging to a corresponding memory bank, according to an interlaced system.

Claims25

Dependent claims

Internal addressing structure for a semiconductor memory having at least two memory banks, comprising:

a plurality of counters, each associated for operation with a corresponding one of the memory banks and capable of generating sequences of digital codes for addressing locations of the corresponding memory bank;
first circuit means for selectively updating the counters;
second circuit means for loading into the counters a common initial digital code, part of an initial address supplied from the outside to the memory through an address line bus, corresponding to an initial memory location;
and
third circuit means capable of detecting a first signal, supplied to the memory from the outside and indicating the presence of a digital code on the bus, to cause the common initial digital code to be loaded into the counters;
and
the first circuit means being capable of identifying, on the basis of the initial address, the bank to which the initial memory location belongs, and of consequently causing the periodic updating of the counters in a sequence which depends on the bank to which the initial memory location belongs, in such a way that successive memory locations preceding or following the initial location are addressed in sequence, each of these successive locations belonging to a corresponding memory bank, according to an interlaced system.

4 more elements

Dependencies are inferred from the claim text.

Internal addressing structure of a semiconductor memory

Life of this patent

Internal addressing structure of a semiconductor memory

Life of this patent

Abstract

Claims25