Apparatus for externally timing high voltage cycles of non-volatile memory system
AssigneeMicron Technology, Inc.
InventorFrankie Fariborz Roohparvar
Life of this patent
Estimating the term…
Abstract
An apparatus which allows the pulse duration of the high voltage pulses used in the programming and erase operations of a non-volatile memory system to be determined by an external timing signal instead of the internal timer normally used. Control of the pulse duration by the internal timer is disabled by gating the timer output signal with the external signal in a manner such that the gate output signal (which triggers the end of the high voltage pulse) is only generated when the external timing signal has a predetermined value. By controlling the value of the external timing signal, the pulse duration can be varied and have values other than those which would result from use of the internal timer.
Claims48
A method for controlling a duration of a high voltage pulse, comprising:
- issuing a first transition of an external timing signal to disable internal control of the duration of the high voltage pulse;
- and
- issuing a second transition of the external timing signal, wherein the time between the act of issuing the first transistion of the external timing signal and the act of issuing the second transition of the external timing signal defines a desired duration of the high voltage pulse.
A system to generate an external timing signal to control a duration of a high voltage pulse, the system comprising:
- a first device to enable external control of a high voltage pulse duration;
- and
- a second device to enable an external timing operation.
A system to generate an external timing signal to control a duration of a high voltage pulse, the system comprising:
- a first flip-flop to enable external control of a high voltage pulse duration;
- and
- a second flip-flop to enable an external timing operation.
A system to generate an external timing signal to control a duration of a high voltage pulse, the system comprising:
- a first flip-flop to enable external control of a high voltage pulse duration;
- a logic device coupled to the first flip-flop;
- and
- a second flip-flop coupled to the logic device to enable an external timing operation.
A system to generate an external timing signal to control a duration of a high voltage pulse, the system comprising:
- a first flip-flop that is receptive to a clock signal and a first code so as to enable external control of the high voltage pulse duration, wherein when the clock signal goes high during a first clock cycle and the first code is high, the first flip-flop produces a flip-flop signal at a logic low level;
- a first logic device coupled to the first flip-flop;
- and
- a second flip-flop coupled to the logic device to produce the external timing signal.
A system to generate an external timing signal to control a duration of a high voltage pulse, the system comprising:
- a first flip-flop that is receptive to a clock signal and a first code so as to enable external control of the high voltage pulse duration, wherein when the clock signal goes high during a first clock cycle and the first code is high, the first flip-flop produces a flip-flop signal at a logic low level;
- a first logic device receptive to the clock signal and the flip-flop signal;
- and
- a second flip-flop coupled to the logic device to produce the external timing signal.
A system to generate an external timing signal to control a duration of a high voltage pulse, the system comprising:
- a first flip-flop that is receptive to a clock signal and a first code so as to enable external control of the high voltage pulse duration, wherein when the clock signal goes high during a first clock cycle and the first code is high, the first flip-flop produces a flip-flop signal at a logic low level;
- a first logic device receptive to the clock signal and the flip-flop signal, wherein the first logic device produces a set signal at a logic low level;
- and
- a second flip-flop coupled to the logic device to produce the external timing signal.
A system to generate an external timing signal to control a duration of a high voltage pulse, the system comprising:
- a first flip-flop that is receptive to a clock signal and a first code signal so as to enable external control of the high voltage pulse duration, wherein when the clock signal goes high during a first clock cycle and the first code signal is high, the first flip-flop produces a flip-flop signal at a logic low level;
- a first logic device receptive to the clock signal, the flip-flop signal, and a second code signal, wherein the first logic device produces a set signal at a logic low level;
- and
- a second flip-flop coupled to the logic device to produce the external timing signal.
A system to generate an external timing signal to control a duration of a high voltage pulse, the system comprising:
- a first flip-flop that is receptive to a clock signal and a first code signal so as to enable external control of the high voltage pulse duration, wherein the first flip-flop produces a flip-flop signal;
- a first logic device receptive to the clock signal, the flip-flop signal, and a second code signal, wherein the first logic device produces a set signal;
- a second logic device receptive to the clock signal, the flip-flop signal and a third code signal, wherein the second logic device produces a reset signal;
- and a second flip-flop coupled to the logic device to produce the external timing signal.
A system to generate an external timing signal to control a duration of a high voltage pulse, the system comprising:
- a first flip-flop that is receptive to a clock signal and a first code signal so as to enable external control of the high voltage pulse duration, wherein the first flip-flop produces a flip-flop signal;
- a first AND gate receptive to the clock signal, the flip-flop signal, and a second code signal, wherein the first logic device produces a set signal;
- a second AND gate receptive to the clock signal, the flip-flop signal and a third code signal, wherein the second logic device produces a reset signal;
- and
- a second flip-flop coupled to the logic device to produce the external timing signal.
Dependencies are inferred from the claim text.