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US 2002/0054533 A1Published application
Semiconductor memory device having SRAM interface
AssigneeFujitsu Limited
InventorHitoshi Ikeda
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a latch circuit which latches an address signal supplied from an exterior of the device, a core circuit which includes memory cells, to which access is made at the address stored in the latch circuit, and a latch timing control circuit which records a fact that the address signal is changed during an operation of the core circuit, and makes the latch circuit latch the changed address signal after a completion of the operation of the core circuit.
Claims10
A semiconductor memory device, comprising:
- a latch circuit which latches an address signal supplied from an exterior of said device;
- a core circuit which includes memory cells, to which access is made at the address stored in said latch circuit;
- and
- a latch timing control circuit which records a fact that a new address signal is received during an operation of said core circuit, and makes said latch circuit latch the new address signal after a completion of the operation of said core circuit.
1 more element
A semiconductor memory device, comprising:
- a core circuit which includes memory cells;
- and
- a timing control circuit which records a fact that a new address signal is supplied from an exterior of said device during an operation of said core circuit, and causes an access operation to be performed on said core circuit based on the new address signal after a completion of the operation of said core circuit.
Dependencies are inferred from the claim text.