Semiconductor memory device having function of supplying stable power supply voltage
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTsukasa Ooishi, Jun Setogawa
Life of this patent
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Abstract
The inventive semiconductor memory device comprises a synchronous circuit formed by a PLL circuit requiring precise operations, an internal circuit group and a VDC circuit. The VDC circuit, a capacitor, a PMOS transistor for a dummy current and an NMOS transistor serving as a high impedance element are arranged for the synchronous circuit. The VDC circuit is arranged for the internal circuit group. The VDC circuit eliminates power supply noise. The PMOS transistor stabilizes the operation of a differential amplifier of the VDC circuit. The capacitor keeps potential difference between a power supply side and a GND side constant. The NMOS transistor stabilizes the voltage on the GND side.
Claims16
A semiconductor memory device comprising:
- an internal circuit including a memory cell array;
- a voltage supply node;
- a synchronous circuit operating on the basis of an operating voltage received from said voltage supply node for generating an internal clock deciding operation timing of said internal circuit;
- a power source for supplying a voltage to said internal circuit and said voltage supply node;
- and
- a voltage stabilizing circuit stabilizing the voltage of said voltage supply node.
A semiconductor memory device comprising:
- a pin;
- an internal circuit, including a memory cell array, operating on the basis of an input from said pin;
- and
- a leakage current prevention circuit provided between said pin and said internal circuit for detecting a leakage current from said internal circuit and electrically disconnecting said pin and said internal circuit from each other.
A semiconductor memory device comprising:
- a pin receiving an input from an external device;
- an internal circuit, including a memory cell array, operating in response to an input from said pin in a normal mode;
- a voltage supply node;
- a synchronous circuit operating on the basis of an operating voltage received from said voltage supply node for generating an internal clock deciding operation timing of said internal circuit;
- and
- a voltage supply control circuit supplying a voltage from said pin to said voltage supply node in a test mode.
Dependencies are inferred from the claim text.