Method and apparatus for refreshing semiconductor memory

A semiconductor memory device, comprising:

• a plurality of memory cell array blocks constructed with a plurality of refresh type memory cells;
• a refresh circuit adapted to generate refresh address signals to refresh the memory cells during a refresh operation;
• row and column decoders adapted to designate addresses to one or more memory cells according to address signals;
• a plurality of sub-word line drivers arranged at the memory cell array blocks in the first direction and shared by two memory cell array blocks;
• a plurality of block sense amplifiers arranged at the memory cell array blocks in the second direction, in perpendicular to that of the first one, and shared by two memory cell array blocks;
• a plurality of circuit blocks constructed with LA drivers respectively arranged at each conjunction area, where areas accommodating sub-word line drivers and block sense amplifiers are crossed, adapted to drive the block sense amplifiers, a PXiD circuit that generates driving control signals to control sub-word line drivers to activate sub-word lines connected with the memory cells;
• and
• a BSYD circuit adapted to selectively enable said LA drivers in response to transmitted block control signals;
• and
• a plurality of block control units arranged correspondingly to the number of circuit blocks and adapted to respectively generate upper and lower block control signals by combining column and row block address decoding signals and simultaneously activating two or more BSYD circuits of the circuit blocks.

A semiconductor memory device, comprising:

• a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks;
• a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks;
• a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed, said conjunction areas comprising:
• one or more LA driver means for driving said block sense amplifiers;
• one or more PXiD circuit means for generating driving control signals to control sub-word line drivers;
• and
• one or more BSYD circuit means for selectively enabling LA drivers in response to transmitted block control signals;
• and
• a plurality of block control unit means for generating upper and lower block control signals.