Semiconductor memory testing method and apparatus
AssigneeAdvantest Corporation
InventorsMakoto Tabata, Noboru Okino
Life of this patent
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Abstract
A testing method which reduces a testing time for a flash memory is proposed. A memory block is subject to an erasure operation by a batch operation. Subsequently, a read-out test is conducted upon the memory block to count the number of unerased memory cells. If the count FN is equal to or greater than a given number TF, a plurality of erasure operations are conducted consecutively next. If FN<TF, a single erasure operation is conducted next, subsequently followed by a read-out test. The erasure operations and the read-out tests are repeated.
Claims13
A semiconductor memory testing method in which a semiconducting memory comprising one or more memory blocks is subject to an erasure operation and a determination whether the semiconductor memory is acceptable or faulty is rendered depending on a result of erasure, comprising the steps of
- applying an erasure operation to every memory cell in one memory block of the semiconductor memory by a batch operation;
- reading out the memory block of the semiconductor memory and counting a number of unerased memory cells;
- and determining a number of erasure operations to be applied next in accordance with the counted number of unerased memory cells.
A semiconductor memory testing apparatus in which a semiconductor memory comprising one or more memory blocks is subject to an erasure operation and a determination is rendered whether a semiconductor memory is acceptable or faulty depending on a result of erasure, comprising
- a pattern generator for generating an address signal, erasure data, a control signal and expected value data;
- a waveform shaper for translating the address signal, the erasure data and the control signal into signals of waveforms which correspond to the specification of the semiconductor memory for application to the semiconductor memory;
- a logic comparator for comparing read-out data which is read out from the semiconductor memory against the expected value to produce an unerased memory cell signal in response to a mismatch therebetween;
- a fail counter for counting the number of unerased memory cell signals occurring;
- a presetter having a preset reference value to be used as a criterion;
- a comparator for comparing the count in the fail counter against the preset value in the presetter;
- and a sequence controller receiving an output from the comparator and for causing the pattern generator to conduct an erasure operation of the semiconductor memory a plurality or times consecutively when the count is greater than the preset value and for causing the pattern generator to conduct an erasure operation of the semiconductor memory once when the count is less than the preset value.
Dependencies are inferred from the claim text.