Semiconductor memory device having a relaxed pitch for sense amplifiers

A semiconductor memory device, comprising:

• a core area including a plurality of memory blocks;
• a data bus including a plurality of data bus lines such that each of said plurality of data bus lines corresponds to one of said plurality of memory blocks, each of said data bus lines carrying a data bit to be written into or read out from a memory cell included in a memory block that corresponds to said data bus line;
• a plurality of input/output terminals provided in number corresponding to said plurality of data bus lines forming said data bus;
• and
• a data path switch circuit provided between said data bus and said input/output terminals for providing interconnection paths of said data bits between said input terminals and said data bus lines,
• said data path switch circuit switching a part of said interconnection paths in response to a switch control signal.