Activation of word lines in semiconductor memory device
AssigneeSeiko Epson Corporation
InventorsKoichi Mizugaki, Eitaro Otsuka
Life of this patent
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Abstract
To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the word line activation controller maintains an activated state of a word line activated during an initial cycle of the consecutive cycles, without deactivating it until a final cycle of the consecutive cycles.
Claims8
A semiconductor memory device comprising:
- at least one memory cell block of memory cells arranged in a matrix, the memory cell block including a plurality of word lines;
- an address input section for input of a multiple-bit address that includes a row address for selecting one of the plurality of word lines;
- a data input/output section for input/output of data corresponding to a memory cell selected by the multiple-bit address;
- and
- a word line activation controller for controlling activation of the word lines;
- wherein the word line activation controller comprises:
- a row address transition detector for detecting whether the row address has changed;
- and wherein when the row address transition detector does not detect a change in the row address during consecutive cycles in which at least one of read and write operations of data for the memory cells are enabled and in which an identical row address is used, the word line activation controller maintains an activated state of a word line activated during an initial cycle of the consecutive cycles, without deactivation thereof until a final cycle of the consecutive cycles.
A method for controlling activation of word lines in a semiconductor memory device comprising:
- at least one memory cell block of memory cells arranged in a matrix, the memory cell block including a plurality of word lines;
- an address input section for input of a multiple-bit address that includes a row address for selecting one of the plurality of word lines;
- and a data input/output section for input/output of data corresponding to a memory cell selected by the multiple-bit address, wherein:
- when no change in the row address is detected during consecutive cycles in which at least one of read and write operations of data for the memory cells are enabled and in which an identical row address is used,
- an activated state of a word line activated during an initial cycle of the consecutive cycles is maintained, without deactivation thereof until a final cycle of the consecutive cycles.
Dependencies are inferred from the claim text.