Semiconductor memory device
AssigneeSeiko Epson Corporation
InventorsSatoshi Inoue, Ichio Yudasaka, Piero Migliorato
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device comprising: an active layer in which are formed a transistor source, channel and drain; a gate for the transistor; a layer of ferroelectric material; and an electrode for applying a voltage to the ferroelectric material; the electrode being spaced apart from the gate, the layer of ferroelectric material having two stable states of internal polarization, and the arrangement being such that the two states of polarization have a detectable difference in effect upon the transfer characteristic of the transistor. The arrangement enables cross-talk between memory cells upon write to be avoided and can mitigate physical interface problems between the ferroelectric material and the active layer.
Claims15
A semiconductor memory device comprising:
- a plurality of memory cells each formed by stacking a plate electrode, a ferroelectric layer, an insulating film, a channel region of a MIS transistor, a gate insulating film of said MIS, and a gate electrode of said MIS transistor in said order,
- wherein a word line is electrically connected to said gate electrode of each of the plurality of memory cells, wherein first and second bit lines are electrically connected to a source region and a drain region of said MIS transistor, respectively, and wherein a plate line is electrically connected to said plate electrode.
A semiconductor memory device comprising:
- an active layer in which are formed a transistor source, channel and drain;
- a gate for the transistor;
- a layer of ferroelectric material;
- and
- an electrode for applying a voltage to the ferroelectric material;
- the electrode being spaced apart from the gate, the layer of ferroelectric material having two stable states of internal polarization, and the arrangement being such that the two states of polarization have a detectable difference in effect upon the transfer characteristic of the transistor.
Dependencies are inferred from the claim text.