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US 2002/0054519 A1Published application
Semiconductor memory and controlling method thereof
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsKatsumi Murai, Jun Horikawa
Life of this patent
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Abstract
The object of the invention is the provision of a semiconductor memory having processor and memory integrally mounted on one chip. To attain the object, crossbar wirings are laid on the memory cell area and crossbar switches are disposed in the sense amplifier area or word driver area. Accordingly, memory sharing is made possible without increasing the chip area and it is also made possible to take out a large number of data continuously. Hence, a memory-embedded system with a high bandwidth can be provided.
Claims16
A semiconductor memory comprising:
- a plurality of memory cells arranged in a matrix array;
- a plurality of bit line pairs each thereof being connected to each column of the plurality of the memory cells;
- a plurality of sense amplifiers of each connected to each bit line pair;
- a plurality of first gate pairs;
- a plurality of second gate pairs;
- a plurality of first data line pairs of each to be connected with one of the bit line pairs selected by means of the first gate pairs, on activation;
- and
- a plurality of second data line pairs of each to be connected with the first data line pair by means of the second gate pairs;
- wherein
- the first data line pair and the second data line pair are arranged to intersect each other.
7 more elements
A semiconductor memory comprising:
- a plurality of memory cells arranged in a matrix array;
- a plurality of bit line pairs each thereof being connected to each column of the plurality of the memory cells;
- a plurality of sense amplifiers of each connected to each bit line pair;
- a plurality of first gate pairs;
- a plurality of second gate pairs;
- a plurality of first data line pairs of each, laid on said memory cell, to be connected with one of the bit line pairs selected by means of the first gate pairs, on activation;
- and
- a plurality of second data line pairs of each, laid on the memory cells, to be connected with one of the first data line pairs by means of the second gate pairs;
- wherein
- the first data line pair and the second data line pair are arranged to intersect with each other.
7 more elements
A semiconductor memory comprising:
- a plurality of memory cells arranged in a matrix array;
- a plurality of bit line pairs each thereof being connected to each column of the plurality of the memory cells;
- a plurality of sense amplifiers of each connected to each bit line pair;
- a plurality of first gates;
- a plurality of second gates;
- a plurality of first data lines of each to be connected with one line of one of the bit line pairs of selected by means of the first gates, on activation;
- and
- a plurality of second data lines of each to be connected with one of the first data lines by means of the second gates;
- wherein
- the first data line and the second data line are arranged to intersect each other.
7 more elements
A semiconductor memory comprising:
- a plurality of memory cells arranged in a matrix array;
- a plurality of bit line pairs each thereof being connected to each column of the plurality of the memory cells;
- a plurality of sense amplifiers of each connected to each bit line pair;
- a plurality of first gate pairs;
- a plurality of second gate pairs;
- a plurality of first data line pairs of each, laid on said memory cell, to be connected with one of the bit line pairs selected by means of the first gate pairs, on activation
- a plurality of first data line pairs of each to be connected on a time sharing basis with one of the bit line pairs selected by means of the first gate pairs, on activation;
- and
- a plurality of second data line pair pairs of each to be connected with the first data line pairs of each by means of the second gate pairs;
- wherein
- the first data line pair and the second data line pair are arranged to intersect each other.
8 more elements
A semiconductor memory comprising:
- one or a plurality of processor elements having arithmetic functions;
- a plurality of memory cells arranged in a matrix array;
- a plurality of bit line pairs each thereof being connected to each column of the plurality of the memory cells;
- a plurality of sense amplifiers of each connected to each bit line pair;
- a plurality of first gate pairs;
- a plurality of second gate pairs;
- a plurality of first data line pairs of each to be connected with one of the bit line pairs selected by means of the first gate pairs, on activation;
- and
- a plurality of second data line pairs to be connected with one of the first data line pairs by means of the second gate pairs;
- wherein
- the first data line pair and the second data line pair are arranged to intersect each other.
8 more elements
A semiconductor memory comprising:
- one or a plurality of processor elements;
- a plurality of memory cells arranged in a matrix array;
- a plurality of bit line pairs each thereof being connected to each column of the plurality of the memory cells;
- a plurality of sense amplifiers of each connected to each bit line pair;
- a plurality of first gates;
- a plurality of second gates;
- a plurality of first data lines of each to be connected with one line of one of the bit line pair of a column selected by means of the first gates, on activation;
- and
- a plurality of second data lines of each to be connected with one of the first data lines by means of the second gates;
- wherein
- the first data line and the second data line are arranged to intersect each other.
8 more elements
A semiconductor memory comprising:
- one or a plurality of processor elements;
- a plurality of memory cells arranged in a matrix array;
- a plurality of bit line pairs each thereof being connected to each column of the plurality of the memory cells;
- a plurality of sense amplifiers of each connected to each bit line pair;
- a plurality of first gates;
- a plurality of second gates;
- a plurality of first data line pairs of each to be connected on a time sharing basis with one of the bit line pair selected by means of the first gate pair, on activation;
- and
- a plurality of second data line pair to be connected with the first data lines pair by means of the second gate pairs;
- wherein
- the first data line pair and the second data line pair are arranged to intersect each other.
8 more elements
A semiconductor memory comprising:
- a plurality of processor elements;
- a plurality of memory cells arranged in a matrix array and organized into a plurality of memory block groups;
- a plurality of bit line pairs each thereof being connected to each column of the plurality of the memory cells;
- a plurality of sense amplifier connected to each bit line pair;
- a plurality of first gate pairs;
- a plurality of second gate pairs;
- a plurality of first data line pairs of each to be connected with one of the bit line pairs selected by means of the first gate pairs, on activation;
- and
- a plurality of second data line pairs of each to be connected with one of the first data line pairs by means of the second gate pairs;
- wherein
- the first data line pair and the second data line pair are arranged to intersect each other.
8 more elements
A semiconductor memory comprising:
- a plurality of processor elements;
- a plurality of memory cells arranged in a matrix array and organized into a plurality of memory block groups;
- a plurality of bit line pairs each thereof being connected to each column of the plurality of the memory cells;
- a plurality of sense amplifiers of each connected to each bit line pair;
- a plurality of first gates;
- a plurality of second gates;
- a plurality of first data lines to be connected with one of the one line of the bit line pairs of a column selected by means of the first gates, on activation;
- and
- a plurality of second data lines to be connected with the first data lines by means of the second gates;
- wherein
- the first data line and the second data line are arranged to intersect each other.
8 more elements
A semiconductor memory comprising:
- one or a plurality of processor elements;
- a plurality of memory cells arranged in a matrix array and organized into a plurality of groups;
- a plurality of bit line pairs each thereof being connected to each column of the plurality of the memory cells;
- a plurality of sense amplifiers of each connected to each bit line pair;
- a plurality of first gate pairs;
- a plurality of second gate pairs;
- a plurality of first data line pairs of each to be connected on a time sharing basis with one of the bit line pairs selected by means of the first gate pairs, on activation;
- and
- a plurality of second data line pairs of each to be connected with one of the first data line pairs by means of the second gate pairs;
- wherein
- the first data line pair and the second data line pair are arranged to intersect each other.
8 more elements
A method for controlling a semiconductor memory comprising the steps of:
- requesting for data communications by processor elements which make data communications with a plurality of memory cells organized into memory block groups;
- controlling data communications in response to the requests for data communications;
- and
- making data communications between the processor elements and the memory cells in accordance with the control signals under the control, wherein, in the step of controlling communications, control signals for controlling each of a plurality of memory cells organized into individual groups are used.
1 more element
Dependencies are inferred from the claim text.