Semiconductor memory device having redundancy
AssigneeMitsubishi Denki Kasbushiki Kaisha
InventorsTSUKASA OOISHI, HIDETO HIDAKA
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Abstract
A redundancy determination circuit receiving an address signal from an address bus outputs a replacement signal when a set address matches the received address. A multiplexer activates any spare activation signal line that activates respective redundant memory arrays provided in the row direction and column direction in a memory bank at a predetermined timing. The redundancy determination circuit can set the address to use a redundant memory array in either the row direction or the column direction. Therefore, the number of redundancy determination circuits can be reduced.
Claims11
A synchronous semiconductor memory device receiving an address signal and a control signal in synchronization with an external clock to input and output storage data, said synchronous semiconductor memory device comprising:
- a plurality of memory cell blocks each having a plurality of memory cells arranged in rows and columns, each of said plurality of memory cell blocks including
- a plurality of regular memory cells,
- a redundant memory cell row provided in a row direction, and
- a redundant memory cell column provided in a column direction;
- an address bus provided common to said plurality of memory cell blocks for transmitting a row address and a column address included in said address signal in a time-divisional manner;
- a plurality of selecting circuits provided corresponding to said memory cell blocks, each for selectively activating one of said redundant memory cell rows and said memory cell columns,
- a plurality of redundancy determination circuits provided corresponding to said memory cell blocks, each for controlling a selecting operation of said selecting circuit based on a detection of whether said address signal from said address bus indicates said row address or said column address according to said control signal and a comparison between said address signal and a preset defective address corresponding to a defective memory cell in said plurality of regular memory cells.
A synchronous semiconductor memory device receiving an externally applied address signal and a control signal in synchronization with an external clock to input and output stored data, said synchronous semiconductor memory device comprising:
- a plurality of memory cell blocks, each having a plurality of memory cells arranged in rows and columns, each of said plurality of memory cell blocks including
- a plurality of regular memory cells, and
- a redundant memory cell;
- an address bus provided common to said plurality of memory cell blocks for transmitting a row address and a column address included in said address signal in a time-divisional manner;
- and
- a redundancy determination circuit provided common to at least two of said plurality of memory cell blocks to detect which one of the corresponding memory cell blocks incorporating an address of said regular memory cell does said address signal from said address bus correspond to according to said control signal, and activating a select operation of a redundant memory cell in said corresponding memory cell block when said address signal matches a preset defective address in said plurality of regular memory cells.
A synchronous semiconductor memory device receiving an externally applied address signal and a control signal in synchronization with an external clock to input and output stored data, said synchronous semiconductor memory device comprising:
- a plurality of memory cell blocks, each having a plurality of memory cells arranged in rows and columns, each of said plurality of memory cell blocks including
- a plurality of regular memory cells,
- a redundant memory cell row provided in a row direction, and
- a redundant memory cell column provided in a column direction;
- a redundancy determination unit including a plurality of redundancy determination circuits for activating a replacement designating signal when said address signal matches a preset defective address in said plurality of regular memory cells;
- an encoder for encoding the replacement designating signal output from said plurality of redundancy determination circuits;
- a replacement designating signal bus for receiving an output of said encoder;
- and
- a plurality of decoders provided corresponding to each of said plurality of memory cell blocks for receiving and decoding the output of said encoder through said replacement designating signal bus, each of said plurality of decoders activating a select operation of any of said redundancy memory cell row and said redundant memory cell column included in each memory block.
Dependencies are inferred from the claim text.