Semiconductor device

A clock synchronous semiconductor device, comprising:

• a plurality of data terminals;
• a plurality of data input buffers provided in association with the plurality of data terminals;
• a clock terminal which receives a clock signal therein;
• and
• memory units each including a plurality of memory cells;
• and
• wherein the operation of writing data into the plurality of memory cells and the operation of reading data from the plurality of memory cells are carried out in response to the clock signal, and
• said each data input buffer is changed from an inactive state to an active state after the reception of a command for providing instructions for the writing of the data into the plurality of memory cells.

A semiconductor device, comprising:

• a plurality of data terminals;
• a plurality of data input buffers provided in association with the plurality of data terminals;
• a clock terminal which receives a clock signal therein;
• a plurality of memory cells each having a select terminal connected to each of word lines and a data input/output terminal connected to each of bit lines;
• and
• a control circuit which controls the operation of writing data into the memory cells and the operation of reading data from the memory cells in synchronism with the clock signal;
• and
• wherein said control circuit provides instructions for a data write operation having specified each bit line based on a column address according to a write command and changes said each data input buffer from an inactive state to an active state after the write command is accepted.

A semiconductor device, comprising:

• a plurality of address input terminals;
• a plurality of address input buffers provided in association with the plurality of address input terminals;
• a clock terminal which receives a clock signal therein;
• a plurality of memory cells each having a select terminal connected to each of word lines and a data input/output terminal connected to each of bit lines;
• and
• a control circuit which controls the operation of writing data into the memory cells and the operation of reading data from the memory cells in synchronism with the clock signal;
• and
• said control circuit provides instructions for a word line selecting operation based on a row address according to a bank active command, provides instructions for a data reading operation having specified each bit line based a column address according to a read command, provides instructions for a data write operation having specified each bit line based on a column address according to a write command and provides instructions for the initialization of each word line according to a precharge command, and changes said address input buffer from an inactive state to an active state after the reception of the bank active command, the read command or the write command and thereafter changes said address input buffer from the active state to the inactive state when waiting for the elapse of a predetermined cycle period synchronized with the clock signal.