Semiconductor memory device and defect remedying method thereof

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• and
• dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines,
• wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said memory cells,
• wherein a number of refresh cycles for refreshing said dynamic memory cells of n bits is a number in a progression expressed as {square root}{square root over (n)}, 2{square root}{square root over (n)}, 4{square root}{square root over (n)}, - - - in at least on operation mode, and
• wherein said n bits are 16 megabits or more.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• and
• dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines,
• wherein each of said dynamic memory cells uses a stacked capacitor,
• wherein a number of refresh cycles for refreshing said dynamic memory cells of n bits is {square root}{square root over (n)} or more in at least one operation mode of the semiconductor memory, and wherein said n bits are 16 megabits or more.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• and
• dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines,
• wherein each of said dynamic memory cells uses a stacked capacitor,
• wherein a number of refresh cycles for refreshing said dynamic memory cells of n bits is a number in a progression expressed as {square root}{square root over (n)}, 2{square root}{square root over (n)}, 4{square root}{square root over (n)}, - - - in at least one operation mode of the semiconductor memory, and
• wherein said n bits are 16 megabits or more.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• and
• dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines, wherein a number of refresh cycles for refreshing said dynamic memory cells of n bits is a number in a progression expressed as 2{square root}{square root over (n)}, 4{square root}{square root over (n)}, 8{square root}{square root over (n)}, - - - in at least one operation mode of the semiconductor memory, and
• wherein said n bits are 16 megabits or more.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines;
• and
• a plurality of sense amplifiers connected to said plurality of bit lines,
• wherein said n bits are 16 megabits or more, wherein the number of activated sense amplifiers per one memory access is {square root}{square root over (n)} or lower, and
• a plurality of bits obtained through said activated sense amplifiers are output as a data.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• and
• dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines,
• wherein said n bits are 16 megabits or more,
• wherein the number of dynamic memory cells connected to a selected word line per one memory access is {square root}{square root over (n)} or lower, and
• a plurality of bits obtained through said activated sense amplifiers are output as data.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines;
• and
• a plurality of sense amplifiers connected to said plurality of bit lines,
• wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode, and
• wherein a first cycle time in said first operation mode is longer than a second cycle time in said second operation mode.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines;
• a plurality of sense amplifiers connected to said plurality of bit lines;
• a first circuit which activates one or more of said plurality of sense amplifiers;
• and
• a second circuit which forms a first timing signal and a second timing signal following said first timing signal,
• wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode,
• wherein said first circuit includes a power switch which is controlled by said first timing signal in said first operation mode, and
• wherein said power switch is controlled by said second timing signal in said second operation mode.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines;
• and
• a plurality of sense amplifiers connected to said plurality of bit lines,
• wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activates sense amplifiers per cycle in a second operation mode,
• wherein said activated sense amplifiers take a first charging time to set corresponding bit lines to a predetermined voltage level in said first operation mode and a second charging time to set corresponding bit lines to said predetermined voltage level in said second operation mode, and
• wherein said first charging time is longer than said second charging time.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines;
• a plurality of sense amplifiers connected to said plurality of bit lines,
• a first circuit which activates one or more of said plurality of sense amplifiers;
• and
• a second circuit which forms a first timing signal and a second timing signal following said first timing signal,
• wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode,
• wherein a first cycle time in said first operation mode is longer than a second cycle time in said second operation,
• wherein said first circuit includes a power switch which is controlled by said first timing signal in said first operation mode, and
• wherein said power switch is controlled by said second timing signal in said second operation mode.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines;
• and
• a plurality of sense amplifiers connected to said plurality of bit lines,
• wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode,
• wherein a first cycle time in said first operation mode is longer than a second cycle time in said second operation,
• wherein said activated sense amplifiers take a first charging time to set corresponding bit lines to a predetermined voltage level in said first operation mode and a second charging time to set corresponding bit lines to said predetermined voltage level in said second operation mode, and
• wherein said first charging time is longer than said second charging time.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines;
• a plurality of sense amplifiers connected to said plurality of bit lines,
• a first circuit which activates one or more of said plurality of sense amplifiers;
• and
• a second circuit which forms a first timing signal and a second timing signal following said first timing signal,
• wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode,
• wherein a first cycle time in said first operation mode is longer than a second cycle time in said second operation,
• wherein said first circuit includes a power switch which is controlled by said first timing signal in said first operation mode,
• wherein said power switch is controlled by said second timing signal in said second operation mode,
• wherein said activated sense amplifiers take a first charging time to set corresponding bit lines to a predetermined voltage level in said first operation mode and a second charging time to set corresponding bit lines to said predetermined voltage level in said second operation mode, and
• wherein said first charging time is longer than said second charging time.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• dynamic memory cells of n bits;
• and
• a plurality of sense amplifiers connected to said plurality of bit lines,
• wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said memory cells,
• wherein the number of activated sense amplifiers per one memory access is {square root over (n)} or lower, and
• wherein said n bits are 16 megabits or more.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• dynamic memory cells of n bits;
• and
• a plurality of sense amplifiers connected to said plurality of bit lines,
• wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said memory cells,
• wherein the number of activated sense amplifiers per one memory access is a number in a progression expressed as {square root over (n)}, {square root over (n)}/2, {square root over (n)}/4, - - - , and
• wherein said n bits are 16 megabits or more.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• dynamic memory cells of n bits;
• and
• a plurality of sense amplifiers connected to said plurality of bit lines,
• wherein each of said dynamic memory cells uses a stacked capacitor,
• wherein the number of activated sense amplifiers per one memory access is {square root}{square root over (n)} or lower, and
• wherein said n bits are 16 megabits or more.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• dynamic memory cells of n bits;
• and
• a plurality of sense amplifiers connected to said plurality of bit lines,
• wherein each of said dynamic memory cells uses a stacked capacitor,
• wherein the number of activated sense amplifiers per one memory access is a number in a progression expressed as {square root over (n)}, {square root over (n)}/2, {square root over (n)}/4, - - - , and
• wherein said n bits are 16 megabits or more.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• dynamic memory cells of n bits;
• and
• a plurality of sense amplifiers connected to said plurality of bit lines,
• wherein the number of activated sense amplifiers per one memory access is a number in a progression expressed as {square root over (n)}/2, {square root over (n)}/4, {square root over (n)}/8, - - - , and
• wherein said n bits are 16 megabits or more.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of dynamic memory cells;
• and
• a plurality of input pins for receiving a row address used for selecting one or more of said plurality of word lines,
• wherein a group of said plurality of input pins are used for receiving a column address so that said semiconductor memory is an address multiplexed type,
• wherein m bits obtained through said dynamic memory cells are output as data,
• wherein m is a number in a progression expressed as 2k, k=2, 3, 4, - - - ,
• wherein a first number of row address bits supplied to said semiconductor memory is larger than a second number of column address bits supplied to said semiconductor memory, and
• wherein the difference between said first number and second number is equal to k.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of dynamic memory cells;
• and
• a plurality of input pins for receiving a row address used for selecting one or more of said plurality of word lines,
• wherein a group of said plurality of input pins are used for receiving a column address so that said semiconductor memory is an address multiplexed type,
• wherein four bits obtained through said dynamic memory cells are output as data, and
• wherein the number of row address bits supplied to said semiconductor memory is larger than the number of column address bits supplied to said semiconductor memory by two.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of dynamic memory cells;
• and
• a plurality of input pins for receiving a row address used for selecting one or more of said plurality of word lines,
• wherein a group of said plurality of input pins are used for receiving a column address so that said semiconductor memory is an address multiplexed type,
• wherein eight bits obtained through said dynamic memory cells are output as data, and
• wherein the number of row address bits supplied to said semiconductor memory is larger than the number of column address bits supplied to said semiconductor memory by three.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of dynamic memory cells;
• and
• a plurality of input pins for receiving a row address used for selecting one or more of said plurality of word lines,
• wherein a group of said plurality of input pins are used for receiving a column address so that said semiconductor memory is an address multiplexed type,
• wherein sixteen bits obtained through said dynamic memory cells are output as data, and
• wherein the number of row address bits supplied to said semiconductor memory is larger than the number of column address bits supplied to said semiconductor memory by four.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of dynamic memory cells;
• and
• a plurality of input pins for receiving a row address used for selecting one or more of said plurality of word lines,
• wherein a group of said plurality of input pins are used for receiving a column address so that said semiconductor memory is an address multiplexed type,
• wherein thirty-two bits obtained through said dynamic memory cells connected to said selected word line are output as data, and
• wherein the number of row address bits supplied to said semiconductor memory is larger than the number of column address bits supplied to said semiconductor memory by five.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of dynamic memory cells;
• and
• a plurality of input pins for receiving a row address used for selecting one or more of said plurality of word lines,
• wherein a group of said plurality of input pins are used for receiving a column address so that said semiconductor memory is an address multiplexed type,
• wherein the number of bits of said row address is larger than the number of bits of said column address, and
• wherein a predetermined pin of said plurality of input pins is used for receiving a bit of the row address and a bit of a predetermined signal other than said column address in a time-series manner.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of dynamic memory cells;
• and
• a plurality of input pins for receiving a row address used for selecting one or more of said plurality of word lines,
• wherein a group of said plurality of input pins are used for receiving a column address so that said semiconductor memory is an address multiplexed type,
• wherein the number of bits of said row address is larger than the number of bits of said column address by two so that four bits are output as data, and
• wherein a predetermined pin of said plurality of input pins is used for receiving a bit of the row address and a bit of a predetermined signal other than said column address in a time-series manner.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of dynamic memory cells;
• and
• a plurality of input pins for receiving a row address used for selecting one or more of said plurality of word lines,
• wherein a group of said plurality of input pins are used for receiving a column address so that said semiconductor memory is an address multiplexed type,
• wherein the number of bits of said row address is larger than the number of bits of said column address by three so that eight bits are output as data, and
• wherein a predetermined pin of said plurality of input pins is used for receiving a bit of the row address and a bit of a predetermined signal other than said column address in a time-series manner.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of dynamic memory cells;
• and
• a plurality of input pins for receiving a row address used for selecting one or more of said plurality of word lines,
• wherein a group of said plurality of input pins are used for receiving a column address so that said semiconductor memory is an address multiplexed type,
• wherein the number of bits of said row address is larger than the number of bits of said column address by four so that sixteen bits are output as data, and
• wherein a predetermined pin of said plurality of input pins is used for receiving a bit of the row address and a bit of a predetermined signal other than said column address in a time-series manner.

A semiconductor memory comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of dynamic memory cells;
• and
• a plurality of input pins for receiving a row address used for selecting one or more of said plurality of word lines,
• wherein a group of said plurality of input pins are used for receiving a column address so that said semiconductor memory is an address multiplexed type,
• wherein the number of bits of said row address is larger than the number of bits of said column address by five so that thirty-two bits are output as data, and
• wherein a predetermined pin of said plurality of input pins is used for receiving a bit of a row address and a bit of a predetermined signal other than said column address in a time-series manner.