US 2002/0054501 A1Published application

Integrated ferroelectric memory having plate lines selected by a column decoder

AssigneeInfineon Technologies AG

InventorsHeinz Honigschmid, Tobias Schlager

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Abstract

An integrated memory in which the plate lines run parallel to the bit lines and are driven by the column decoder. The effect achieved by the fact that each plate line is connected to the memory cells of the associated bit line is that only those memory cells whose associated bit line is required for the respective memory access are affected by the pulsed signals of the plate line. Therefore, only the potential of that bit line which is currently required for a data transfer is influenced by pulsed signals on the associated plate lines.

Claims7

Dependent claims

An integrated memory, comprising:

bit lines;
word lines;
crossover points where said bit lines crossover said word lines;
memory cells that are configured at said crossover points, each one of said memory cells including at least one selection transistor having a control terminal that is connected to one of said word lines, each one of said memory cells including a storage capacitor having a first electrode that is remote from said selection transistor and a second electrode, said selection transistor connecting said second electrode of said storage capacitor to one of said bit lines;
plate lines for carrying pulsed signals, each one of said plate lines connected to said first electrode of said storage capacitor of a respective one of said memory cells, said plate lines configured parallel to said bit lines;
a row decoder for addressing said word lines;
a column decoder for selecting at least one of said plate lines in dependence on a column address;
sense amplifiers for amplifying data that are read from said memory cells, each one of said sense amplifiers are respectively connected to at least two of said bit lines which are assigned different column addresses;
control units for performing a function that is selected from the group consisting of supplying input signals to said sense amplifiers, forwarding output signals from said sense amplifiers, and activating said sense amplifiers, said control units including first switching elements and second switching elements;
and
data lines for transferring the data that have been read from said memory cells and that have been amplified by said sense amplifiers, said second switching elements connecting said data lines to said sense amplifiers;
a respective one of said plate lines and at least one of said bit lines are connected to a given one of said memory cells;
said sense amplifiers are connected to a respective one of said bit lines by a respective one of said first switching elements;
each one of said first switching elements including a control terminal that is connected to said column decoder;
each one of said second switching elements including a control terminal;
said plate lines defining groups of said plate lines;
each one of said groups of said plate lines is respectively assigned to said at least two of said bit lines that are connected to a respective one of said sense amplifiers;
and
each one of said groups of said plate lines is connected, using an OR function, to said control terminal of one of said second switching elements, said one of said second switching elements is connected to a respective one of said sense amplifiers.

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Dependencies are inferred from the claim text.

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Abstract

An integrated memory, comprising:

bit lines;
word lines;
crossover points where said bit lines crossover said word lines;
memory cells that are configured at said crossover points, each one of said memory cells including at least one selection transistor having a control terminal that is connected to one of said word lines, each one of said memory cells including a storage capacitor having a first electrode that is remote from said selection transistor and a second electrode, said selection transistor connecting said second electrode of said storage capacitor to one of said bit lines;
plate lines for carrying pulsed signals, each one of said plate lines connected to said first electrode of said storage capacitor of a respective one of said memory cells, said plate lines configured parallel to said bit lines;
a row decoder for addressing said word lines;
a column decoder for selecting at least one of said plate lines in dependence on a column address;
sense amplifiers for amplifying data that are read from said memory cells, each one of said sense amplifiers are respectively connected to at least two of said bit lines which are assigned different column addresses;
control units for performing a function that is selected from the group consisting of supplying input signals to said sense amplifiers, forwarding output signals from said sense amplifiers, and activating said sense amplifiers, said control units including first switching elements and second switching elements;
and
data lines for transferring the data that have been read from said memory cells and that have been amplified by said sense amplifiers, said second switching elements connecting said data lines to said sense amplifiers;
a respective one of said plate lines and at least one of said bit lines are connected to a given one of said memory cells;
said sense amplifiers are connected to a respective one of said bit lines by a respective one of said first switching elements;
each one of said first switching elements including a control terminal that is connected to said column decoder;
each one of said second switching elements including a control terminal;
said plate lines defining groups of said plate lines;
each one of said groups of said plate lines is respectively assigned to said at least two of said bit lines that are connected to a respective one of said sense amplifiers;
and
each one of said groups of said plate lines is connected, using an OR function, to said control terminal of one of said second switching elements, said one of said second switching elements is connected to a respective one of said sense amplifiers.

16 more elements