System and method for eliminating pulse width variations in digital delay lines

Abstract

A system and method for eliminating pulse width variations in digital delay lines comprises partitioning the delay line into two substantially identical blocks of delay inverters and inserting a first inverter between the two blocks and a second substantially identical inverter at the output of the second block. In this manner the requirement for matching device characteristics at the individual delay inverter level is eliminated and the only requirement is that the parasitic loading of the inverter between the blocks and the inverter on the output of the second block be the same. Consequently, the layout of the delay inverters in a single block may be effectuated in the most efficient manner possible and the same identical layout can be used for the first and second blocks. Since the rising edge input to the first block becomes a falling edge input to the second block as it propagates through the delay line, the rising and falling input edges will encounter an identical set of transitions as they propagate through the two blocks. If the loading of the inverter at the output of the first block and that of the inverter at the output of the second block are identical, the pulse width will be perfectly preserved.

Dependencies are inferred from the claim text.