Back to results
US 2002/0053931 A1Published application
Phase difference signal generator and multi-phase clock signal generator having phase interpolator
AssigneeNEC Corporation
InventorKouichi Yamaguchi
Life of this patent
Estimating the term…
Abstract
In a phase difference signal generator, a first delay circuit has a delay time of nx where n ix 2, 3, . . . and x is a voluntary real number, the delay circuit receiving a first input clock signal having a phase of 0° to generate a first phase difference signal. At least one k-to-(n-k) weighted phase interpolator has a first input for receiving an output signal of said first delay circuit and a second input for receiving a second input clock signal having a phase of θ to generate an output signal having a phase of (n-k)x+kθ/n where k is 1, 2, . . . , n-1. At least one second delay circuit is connected to the k-to-(n-k) weighted phase interpolator. The second delay circuit has a delay time of kx to generate a k-th phase difference signal.
Claims14
A phase difference signal generator comprising:
- a first delay circuit having a delay time of nx where n is 2, 3, . . . and x is a voluntary real number, said first delay circuit receiving a first input clock signal having a phase of 0° to generate a first phase difference signal;
- at least one k-to-(n-k) weighted phase interpolator having a first input for receiving an output signal of said first delay circuit and a second input for receiving a second input clock signal having a phase of θ to generate an output signal having a phase of (n-k)x+kθ/n where k is 1, 2, . . . , n-1;
- and
- at least one second delay circuit connected to said k-to-(n-k) weighted phase interpolator, said second delay circuit having a delay time of kx to generate a k-th phase difference signal.
1 more element
A phase difference signal generator comprising:
- a first delay circuit having a delay time of x where x is a voluntary real number, said first delay circuit receiving a first input clock signal having a phase of 0° to generate a first phase difference signal having a phase of x;
- a second delay circuit having a delay time of x, connected to said first delay circuit;
- and
- a 1-to-1 weighted phase interpolator having a first input for receiving an output signal of said second delay circuit and a second input for receiving a second input clock signal having a phase of θ to generate a second phase difference signal having a phase of x+θ/2.
1 more element
A phase difference signal generator comprising:
- a first delay circuit having a delay time of x where x is a voluntary real number, said first delay circuit receiving an input clock signal having a phase of 0° to generate a first phase difference signal having a delay time of x;
- a second delay circuit having a delay time of x, connected to said first delay circuit;
- an inverter for receiving said input clock signal;
- and
- a 1-to-1 weighted phase interpolator having a first input for receiving an output signal of said second delay circuit and a second input for receiving an output signal of said inverter to generate a second phase difference signal having a phase of x+90°
2 more elements
A multi-phase clock signal generator comprising:
- a first phase difference signal generator for receiving first and second input clock signals having phases of 0° and 180° , respectively, to generate first and second output clock signals having phases of 0°+x and 90°+x, respectively, where x is a voluntary real number;
- and
- a second phase difference signal generator for receiving said second and first input clock signals to generate third and fourth output clock signals having phases of 180°+x and 270°+x,
- each of said first and second phase difference signal generators comprising:
- a first delay circuit having a delay time of 2x for receiving one of said input clock signals to generate one of said first and third output clock signals
- a 1-to-1 weighted phase interpolator having a first input for receiving an output signal of said first delay circuit and a second input for receiving the other of said first and second input clock signals to generate an output signal having one phase of x+90° and 270°+x;
- and
- a second delay circuit connected to said 1-to-1 weighted phase interpolator, said second delay circuit having a delay time of x to generate one of said second and fourth output clock signals.
5 more elements
A multi-phase clock signal generator comprising:
- a first phase difference signal generator for receiving first and second input clock signals having phases of 0° and 180°, respectively, to generate first and second output clock signals having phases of 0°+x and 90°+x, respectively, where x is a voluntary real number;
- and a second phase difference signal generator for receiving said second and first input clock signals to generate third and fourth output clock signals having phases of 180°+x and 270°+x,
- each of said first and second phase difference signal generators comprising:
- a first delay circuit having a delay time of x to receive one of first and second input clock signals to generate one of said first and third output clock signals,
- a second delay circuit having a delay time of x, connected to said first delay circuit;
- and
- a 1-to-1 weighted phase interpolator having a first input for receiving an output signal of said second delay circuit and a second input for receiving the other of said first and second input clock signals to generate one of said second and fourth output clock signals.
4 more elements
A multi-phase clock signal generator comprising n phase difference signal generator stages each including 2n phase difference signal generators where n is 2, 3, . . . ,
- each of two phase difference signal generators of a first one of said phase difference signal generator stages receiving two input clock signals having phases of 0° and 180°, respectively;
- each of 2k phase difference signal generators of a k-th one of said phase difference signal generator stages receiving two output signals of a (k-1)-th one of said phase difference signal generator stage where k is 2, 3, . . . , n,
- 2n phase difference signal generators of an n-th one of said phase difference signal generator stages generating output clock signals having a phase of 360°/n with each other,
- each of said phase difference generators comprising:
- first and second input terminals;
- first and second output terminals;
- a first delay circuit, connected between said first input terminal and said first output terminal, said first delay circuit having a delay time of x where x is a voluntary real number;
- a 1-to-1 weighted phase interpolator having a first input connected to said first delay circuit and a second input connected to said second input terminal;
- and
- a second delay circuit connected between said 1-to-1 weighted phase interpolator and said second output terminal and having a delay time of x.
7 more elements
A multi-phase clock signal generator comprising n phase difference signal generator stages each including 2n phase difference signal generators where n is 2, 3, . . . ,
- each of two phase difference signal generators of a first one of said phase difference signal generator stages receiving two input clock signals having phases of 0° and 180°, respectively;
- each of 2k phase difference signal generators of a k-th one of said phase difference signal generator stages receiving two output signals of a (k-1)-th one of said phase difference signal generator stage where k is 2, 3, . . . , n,
- 2n phase difference signal generators of an n-th one of said phase difference signal generator stages generating output clock signals having a phase of 360°/n with each other,
- each of said phase difference generators comprising:
- first and second input terminals;
- first and second output terminals;
- a first delay circuit, connected between said first input terminal and said first output terminal, said first delay circuit having a delay time of x where x is a voluntary real number;
- a second delay circuit, connected to said first delay circuit, said second delay circuit having a delay time of x:
- and
- a 1-to-1 weighted phase interpolator having a first, input connected to said second delay circuit and a second input connected to said second input terminal.
7 more elements
Dependencies are inferred from the claim text.