BICMOS semiconductor integrated circuit device and fabrication process thereof

A BICMOS semiconductor integrated circuit device, comprising a semiconductor substrate having an insulating layer internally and partially embedded therein and a plurality of semiconductor layers deposited on said insulating layer, an n channel insulated gate type transistor and a p channel insulated gate type transistor each formed in said plurality of semiconductor layers, a highly-doped collector layer of a bipolar transistor formed by doping impurities on a said-insulating-layer-free portion of the surface of said semiconductor substrate, a low-doped collector layer of the bipolar transistor deposited on said highly-doped collector layer to have a height level substantially equal to that of the upper surface of said semiconductor layer, and a base layer deposited over the upper surface of said low-doped collector layer.

A BICMOS semiconductor integrated circuit device, comprising a semiconductor substrate having an insulating layer internally and partially embedded therein and a plurality of semiconductor layers deposited on said insulating layer, an n channel insulated gate type transistor and a p channel insulated gate type transistor each formed in said plurality of semiconductor layers, a highly-doped collector layer of a bipolar transistor formed by doping impurities on a said-insulating-layer-free portion of the surface of said semiconductor substrate, and a low-doped collector layer of the bipolar transistor deposited over said highly-doped collector layer to have a height level higher than that of the upper surface of said semiconductor layer.

A BICMOS semiconductor integrated circuit device comprising a semiconductor substrate having an insulating layer internally and partially embedded therein and a plurality of semiconductor layers deposited on said insulating layer, an n channel insulated gate type transistor and a p channel insulated gate type transistor each formed in said plurality of semiconductor layers, a highly-doped collector layer of a vertical bipolar transistor formed in a said-insulating-layer-free portion of said semiconductor substrate, a low-doped collector layer deposited on said highly-doped collector layer, and a base layer and an emitter layer each formed on the upper surface portion of said low-doped collector layer, wherein said low-doped collector layer between said base layer and said highly-doped collector layer has a thickness not less than the total thickness of said insulating layer and said semiconductor layer.

A BICMOS semiconductor integrated circuit device comprising a buried insulating layer partially disposed on a semiconductor region, a plurality of semiconductor layers deposited on said insulating layer and having a thickness not greater than 0.15 μm, a plurality of n type and p type insulated gate type transistors formed in said semiconductor layer, and a vertical bipolar transistor which has a highly-doped collector layer formed in a said-insulating-layer-free portion of said semiconductor region, a low-doped collector layer disposed above said highly-doped collector layer, and base and emitter layers each disposed on the upper surface portion of said low-doped collector layer, and has a collector-emitter breakdown voltage of 2 V or greater.

A process for fabricating a semiconductor integrated circuit device, which comprises preparing a semiconductor wafer having an insulating layer embedded in a semiconductor region and a semiconductor layer deposited on said insulating layer, partially removing said semiconductor layer and said insulating layer therebelow to expose said semiconductor region below said semiconductor layer and said insulating layer, forming a buried highly-doped collector layer for a vertical bipolar transistor by ion implantation inside of said exposed semiconductor region, forming at least a part of a low-doped collector layer at a site inside of said semiconductor layer and over said buried highly-doped collector layer, and forming a base layer and an emitter layer each at the surface portion of said low-doped collector layer.

A process for fabricating a semiconductor integrated circuit device, which comprises preparing a semiconductor wafer having an insulating layer embedded in a semiconductor region and a semiconductor layer deposited on said insulating layer, partially forming a buried highly-doped collector layer by ion implantation, through said semiconductor layer and said insulating layer therebelow, inside of said semiconductor region below said semiconductor layer and said insulating layer, removing said semiconductor layer and said insulating layer on said buried highly-doped collector layer, forming a low-doped collector layer over said highly-doped collector layer, and forming a base layer and an emitter layer each at the surface portion of said low-doped collector layer.