Semiconductor transistor with multi-depth source drain

A method of fabricating a semiconductor structure wherein said structure comprises a diffusion region having at least two regions of different depth, the deepest of which is aligned to an adjacent trench isolation region, said method comprising the steps of:

• (a) providing a semiconductor structure having a recess, divot or both formed therein, said FET structure further comprising at least a shallow trench isolation region and an extension embedded in a semiconductor substrate;
• (b) forming a masking material on the surface of the structure whereby the area at the shallow trench isolation region and the extension is left exposed;
• (c) doping through the exposed areas of the masking material, wherein said doping forms a diffusion region having at least two areas of different depth, the deepest of which is aligned to the shallow trench isolation;
• (d) removing the masking material;
• and
• (e) forming a silicide layer on said semiconductor substrate so as to form a contact between the diffusion region and any adjacent external device region.

A semiconductor structure comprising:

• a semiconductor substrate having a surface;
• an external device region on the surface of said semiconductor substrate;
• a channel region of a first dopant type in said semiconductor substrate under said FET;
• and
• a doped region of a second dopant type in said substrate, said doped region comprising a first portion abutting said channel region, of a first depth, a second portion abutting said first portion, of a second depth which is deeper than the depth of the first portion.