Reduced topography DRAM cell fabricated using a modified logic process and method for operating same

A dynamic random access memory (DRAM) cell comprising:

• a semiconductor substrate having a first conductivity type;
• a field dielectric region located in the semiconductor substrate, the field dielectric extending below an upper surface of the semiconductor substrate and having a cavity located therein, the cavity extending below the upper surface and exposing a first portion of the semiconductor substrate at a sidewall of the cavity;
• a crown electrode located in the cavity, the crown electrode having a base region located at the bottom of the cavity and sidewall regions located along the sidewalls of the cavity, the crown electrode contacting the first portion of the semiconductor substrate;
• a contact region having a second conductivity type, opposite the first conductivity type, located in the first portion of the semiconductor substrate and providing an electrical connection to the crown electrode;
• a capacitor dielectric layer located over the crown electrode;
• a plate electrode located over the capacitor dielectric layer, wherein the plate electrode is located substantially within the cavity;
• a gate dielectric layer located over the upper surface of the semiconductor substrate;
• a gate electrode formed over the gate dielectric layer;
• and
• a source region and a drain region of the second conductivity type located in the semiconductor substrate and aligned with the gate electrode, wherein the source region is continuous with the contact region.

A memory system that operates in response to a positive supply voltage and a ground supply voltage, the memory system comprising:

• a dynamic random access memory (DRAM) cell having an access transistor and a capacitor structure;
• a word line coupled to the gate electrode, wherein the word line is activated to access the DRAM cell;
• a word line driver coupled to the word line;
• and
• a positive boosted voltage generator for providing a positive boosted voltage greater than the positive supply voltage and less than one diode voltage drop greater than the positive supply voltage, the positive boosted voltage generator being coupled to the word line driver.

A memory system that operates in response to a positive supply voltage and a ground supply voltage, the memory system comprising:

• a dynamic random access memory (DRAM) cell having an access transistor and a capacitor structure;
• a word line coupled to the DRAM cell, wherein the word line is activated to access the DRAM cell;
• a word line driver coupled to the word line;
• and
• a negative boosted voltage generator for providing a negative boosted voltage less than the ground supply voltage by a voltage less than the absolute value of one diode voltage drop, wherein the negative boosted voltage generator is coupled to the word line driver.