Electro-optical device and method of manufacturing the same

An electrical device comprising an n-channel TFT and a p-channel TFT, comprising:

• a semiconductor layer on an insulating surface;
• a gate insulating film on the semiconductor layer;
• and
• a gate electrode on the gate insulating film,
• wherein the semiconductor layer in the p-channel TFT includes a channel forming region, first impurity regions containing an n-type impurity element and a p-type impurity element, and a second impurity region containing only a p-type impurity element,
• wherein the second impurity region is sandwiched between a pair of the first impurity regions, and
• wherein a wiring line for electrically connecting the p-channel TFT to another TFT is connected to the second impurity region in the p-channel TFT.

A method of manufacturing an electrical device, comprising steps of:

• forming an amorphous semiconductor layer on an insulating surface;
• doping the amorphous semiconductor layer with a catalytic element for promoting crystallization;
• heating the amorphous semiconductor layer doped with the catalytic element to obtain a crystalline semiconductor layer;
• forming a gate insulating film on the crystalline semiconductor layer;
• forming a conductive film on the gate insulating film;
• etching the conductive film to form a gate electrode of an n-channel TFT and to form a conductive pattern for a p-channel TFT;
• doping the semiconductor layer with an n-type impurity element while using the gate electrode and the conductive pattern as masks;
• etching the conductive pattern to form a gate electrode of the p-channel TFT while covering a region that is used for the n-channel TFT with a resist mask;
• and
• doping the semiconductor layer in the p-channel TFT with a p-type impurity element.

A method of manufacturing an electrical device, comprising steps of:

• forming an amorphous semiconductor layer on an insulating surface;
• doping the amorphous semiconductor layer with a catalytic element for promoting crystallization;
• heating the amorphous semiconductor layer doped with the catalytic element and then irradiating the semiconductor layer with a laser to obtain a crystalline semiconductor layer;
• forming a gate insulating film on the crystalline semiconductor layer;
• forming a conductive film on the gate insulating film;
• etching the conductive film to form a gate electrode of an n-channel TFT and to form a conductive pattern for a p-channel TFT;
• doping the semiconductor layer with an n-type impurity element while using the gate electrode and the conductive pattern as masks;
• etching the conductive pattern to form a gate electrode of the p-channel TFT while covering a region that is used for the n-channel TFT with a resist mask;- and
• doping the semiconductor layer in the p-channel TFT with a p-type impurity element.

A method of manufacturing an electrical device, comprising steps of:

• forming an amorphous semiconductor layer on an insulating surface;
• doping the amorphous semiconductor layer with a catalytic element for promoting crystallization;
• heating the amorphous semiconductor layer doped with the catalytic element to obtain a crystalline semiconductor layer;
• forming a gate insulating film on the crystalline semiconductor layer;
• forming a first conductive film and a second conductive film on the gate insulating film;
• etching the first conductive film and the second conductive film to form first shape gate electrodes;
• doping the semiconductor layer with an n-type impurity element while using the first shape gate electrodes as masks;
• etching the first shape gate electrodes to form second shape gate electrodes narrower than the first shape gate electrodes;
• doping the semiconductor layer with an n-type impurity element while using the second shape gate electrodes as masks;
• etching the second shape gate electrodes to form third shape gate electrodes;
• etching the third shape gate electrodes to form fourth shape gate electrodes;
• and
• doping the semiconductor layer in the p-channel TFT with a p-type impurity element while using the fourth shape gate electrodes as masks.

A method of manufacturing an electrical device, comprising steps of:

• forming an amorphous semiconductor layer on an insulating surface;
• doping the amorphous semiconductor layer with a catalytic element for promoting crystallization;
• heating the amorphous semiconductor layer doped with the catalytic element and then irradiating the amorphous semiconductor layer with a laser to obtain a crystalline semiconductor layer;
• forming a gate insulating film on the crystalline semiconductor layer;
• forming a first conductive film and a second conductive film on the gate insulating film;
• etching the first conductive film and the second conductive film to form first shape gate electrodes;
• doping the semiconductor layer with an n-type impurity element while using the first shape gate electrodes as masks;
• etching the first shape gate electrodes to form second shape gate electrodes narrower than the first shape gate electrodes;
• doping the semiconductor layer with an n-type impurity element while using the second shape gate electrodes as masks;
• etching the second shape gate electrodes to form third shape gate electrodes;
• etching the third shape gate electrodes to form fourth shape gate electrodes;
• and
• doping the semiconductor layer in the p-channel TFT with a p-type impurity element while using the fourth shape gate electrodes as masks.

A method of manufacturing an electrical device, comprising steps of:

• forming an amorphous semiconductor layer on an insulating surface;
• doping the amorphous semiconductor layer with a catalytic element for promoting crystallization;
• heating the amorphous semiconductor layer doped with the catalytic element to obtain a crystalline semiconductor layer;
• forming a gate insulating film on the crystalline semiconductor layer;
• forming a first conductive film and a second conductive film on the gate insulating film;
• etching the first and second conductive films to form a first gate electrode and a second gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the first and second gate electrodes;
• etching the first and second gate electrodes to form a third gate electrode and a fourth gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the third and fourth gate electrodes;
• etching the fourth gate electrode to form a fifth gate electrode for a p-channel TFT while covering an n-channel TFT with a resist mask;
• and
• doping the semiconductor layer in the p-channel TFT with a p-type impurity element while using the fifth gate electrode as a mask.

A method of manufacturing an electrical device, comprising steps of:

• forming an amorphous semiconductor layer on an insulating surface;
• doping the amorphous semiconductor layer with a catalytic element for promoting crystallization;
• heating the amorphous semiconductor layer doped with the catalytic element and then irradiating the amorphous semiconductor layer with a laser to obtain a crystalline semiconductor layer;
• forming a gate insulating film on the crystalline semiconductor layer;
• forming a first conductive film and a second conductive film on the gate insulating film;
• etching the first conductive film and the second conductive film to form a first gate electrode (A) and a second gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the first gate electrode and the second gate electrode;
• etching the first gate electrode and the second gate electrode to form a third gate electrode and a fourth gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the third gate electrode and the fourth gate electrode;
• etching the fourth gate electrode to form a fifth gate electrode for a p-channel TFT while covering an n-channel TFT with a resist mask;
• and
• doping the semiconductor layer in the p-channel TFT with a p-type impurity element while using the fifth gate electrode as a mask.

A method of manufacturing an electrical device, comprising steps of:

• forming an amorphous semiconductor layer on an insulating surface;
• doping the amorphous semiconductor layer with a catalytic element for promoting crystallization;
• heating the amorphous semiconductor layer doped with the catalytic element to obtain a crystalline semiconductor layer;
• forming a gate insulating film on the crystalline semiconductor layer;
• forming first and second conductive films on the gate insulating film;
• etching the first and second conductive film to form a first gate electrode, a second gate electrode, and a third gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the first, second, and third gate electrodes;
• etching the first, second, and third gate electrodes to form a fourth gate electrode, a fifth gate electrode, and a sixth gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the fourth gate electrode, the fifth gate electrode, and the sixth gate electrode;
• etching the fifth gate electrode and the sixth gate electrode to form a seventh gate electrode for a p-channel TFT and an eighth gate electrode for a pixel TFT, respectively, while covering with a resist mask an n-channel TFT that is formed in a driving circuit;
• etching the fifth gate electrode to form a ninth gate electrode;
• and
• doping the semiconductor layer in the p-channel TFT with a p-type impurity element while using the ninth gate electrode as a mask.

A method of manufacturing an electrical device, comprising steps of:

• forming an amorphous semiconductor layer on an insulating surface;
• doping the amorphous semiconductor layer with a catalytic element for promoting crystallization;
• heating the amorphous semiconductor layer doped with the catalytic element to obtain a crystalline semiconductor layer;
• forming a gate insulating film on the crystalline semiconductor layer;
• forming a first conductive film and a second conductive film on the gate insulating film;
• etching the first conductive film and the second conductive film to form a first gate electrode, a second gate electrode, and a third gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the first gate electrode, the second gate electrode, and the third gate electrode;
• etching the first gate electrode, the second gate electrode, and the third gate electrode to form a fourth gate electrode, a fifth gate electrode, and a sixth gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the fourth gate electrode, the fifth gate electrode, and the sixth gate electrode;
• etching the fifth gate electrode of a p-channel TFT and the sixth gate electrode of a pixel TFT to form a seventh gate electrode and an eighth gate electrode, respectively, while covering with a resist mask an n-channel TFT that is formed in a driving circuit;
• etching the seventh gate electrode to form a ninth gate electrode;
• doping the semiconductor layer in the p-channel TFT with a p-type impurity element while using the ninth gate electrode as a mask;
• subjecting the insulator to heat treatment;
• covering the entire surface with an inorganic interlayer insulating film;
• forming an organic interlayer insulating film on the inorganic interlayer insulating film;
• forming a contact hole reaching the semiconductor layer through the inorganic interlayer insulating film and the organic interlayer insulating film;
• forming a pixel electrode on the organic interlayer insulating film;
• and
• forming a connection wiring line.

A method of manufacturing an electrical device, comprising steps of:

• forming an amorphous semiconductor layer on an insulating surface;
• doping the amorphous semiconductor layer with a catalytic element for promoting crystallization;
• heating the amorphous semiconductor layer doped with the catalytic element to obtain a crystalline semiconductor layer;
• forming a gate insulating film on the crystalline semiconductor layer;
• forming a first conductive film and a second conductive film on the gate insulating film;
• etching the first conductive film and the second conductive film to form a first gate electrode, a second gate electrode, and a third gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the first gate electrode, the second gate electrode, and the third gate electrode;
• etching the first gate electrode, the second gate electrode, and the third gate electrode to form a fourth gate electrode, a fifth gate electrode, and a sixth gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the fourth gate electrode, the fifth gate electrode, and the sixth gate electrode;
• etching the fifth gate electrode of a p-channel TFT and the sixth gate electrode of a pixel TFT to form a seventh gate electrode and an eighth gate electrode, respectively, while covering with a resist mask an n-channel TFT that is formed in a driving circuit;
• etching the seventh gate electrode to form a ninth gate electrode;
• doping the semiconductor layer in the p-channel TFT with a p-type impurity element while using the ninth gate electrode as a mask;
• covering the entire surface with an inorganic interlayer insulating film;
• gettering the catalytic element through heat treatment;
• forming an organic interlayer insulating film on the inorganic interlayer insulating film;
• forming a contact hole reaching the semiconductor layer through the inorganic interlayer insulating film and the organic interlayer insulating film;
• forming a pixel electrode on the organic interlayer insulating film;
• and
• forming a connection wiring line.

A method of manufacturing an electrical device, comprising steps of:

• forming an amorphous semiconductor layer on an insulating surface;
• doping the amorphous semiconductor layer with a catalytic element for promoting crystallization;
• heating the amorphous semiconductor layer doped with the catalytic element and then irradiating the semiconductor layer with a laser to obtain a crystalline semiconductor layer;
• forming a gate insulating film on the crystalline semiconductor layer;
• forming a first conductive film and a second conductive film on the gate insulating film;
• etching the first conductive film and the second conductive film to form a first gate electrode, a second gate electrode, and a third gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the first gate electrode, the second gate electrode, and the third gate electrode;
• etching the first gate electrode, the second gate electrode, and the third gate electrode to form a fourth gate electrode, a fifth gate electrode, and a sixth gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the fourth gate electrode, the fifth gate electrode, and the sixth gate electrode;
• etching the fifth gate electrode of a p-channel TFT and the sixth gate electrode of a pixel TFT to form a seventh gate electrode and an eighth gate electrode, respectively, while covering with a resist mask an n-channel TFT that is formed in a driving circuit;
• etching the seventh gate electrode to form a ninth gate electrode;
• doping the semiconductor layer in the p-channel TFT with a p-type impurity element while using the ninth gate electrode as a mask;
• subjecting the insulator to heat treatment;
• covering the entire surface with an inorganic interlayer insulating film;
• forming an organic interlayer insulating film on the inorganic interlayer insulating film;
• forming a contact hole reaching the semiconductor layer through the inorganic interlayer insulating film and the organic interlayer insulating film;
• forming a pixel electrode on the organic interlayer insulating film;
• and
• forming a connection wiring line.

A method of manufacturing an electrical device, comprising steps of:

• forming an amorphous semiconductor layer on an insulating surface;
• doping the amorphous semiconductor layer with a catalytic element for promoting crystallization;
• heating the amorphous semiconductor layer doped with the catalytic element and then irradiating the semiconductor layer with a laser to obtain a crystalline semiconductor layer;
• forming a gate insulating film on the crystalline semiconductor layer;
• forming a first conductive film and a second conductive film on the gate insulating film;
• etching the first conductive film and the second conductive film to form a first gate electrode, a second gate electrode, and a third gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the first gate electrode, the second gate electrode, and the third gate electrode;
• etching the first gate electrode, the second gate electrode, and the third gate electrode to form a fourth gate electrode, a fifth gate electrode, and a sixth gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the fourth gate electrode, the fifth gate electrode, and sixth the gate electrode;
• etching the fifth gate electrode of a p-channel TFT and the sixth gate electrode of a pixel TFT to form a seventh gate electrode and an eighth gate electrode, respectively, while covering with a resist mask an n-channel TFT that is formed in a driving circuit;
• etching the seventh gate electrode to form a ninth gate electrode;
• doping the semiconductor layer in the p-channel TFT with a p-type impurity element while using the ninth gate electrode as a mask;
• covering the entire surface with an inorganic interlayer insulating film;
• gettering the catalytic element through heat treatment;
• forming an organic interlayer insulating film on the inorganic interlayer insulating film;
• forming a contact hole reaching the semiconductor layer through the inorganic interlayer insulating film and the organic interlayer insulating film;
• forming a pixel electrode on the organic interlayer insulating film;
• and
• forming a connection wiring line.

A method of manufacturing an electrical device, comprising steps of:

• forming an amorphous semiconductor layer on an insulating surface;
• doping the amorphous semiconductor layer with a catalytic element for promoting crystallization;
• heating the amorphous semiconductor layer doped with the catalytic element to obtain a crystalline semiconductor layer;
• forming a gate insulating film on the crystalline semiconductor layer;
• forming a first conductive film and a second conductive film on the gate insulating film;
• etching the first conductive film and the second conductive film to form a first gate electrode, a second gate electrode, and a third gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the first gate electrode, the second gate electrode, and the third gate electrode;
• etching the first gate electrode, the second gate electrode, and the third gate electrode to form a fourth gate electrode, a fifth gate electrode, and a sixth gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the fourth gate electrode, the fifth gate electrode, and the sixth gate electrode;
• etching the fifth gate electrode of a p-channel TFT and the sixth gate electrode of a pixel TFT to form a seventh gate electrode and an eighth gate electrode, respectively, while covering with a resist mask an n-channel TFT that is formed in a driving circuit;
• etching the seventh gate electrode to form a ninth gate electrode;
• removing the gate insulating film while using the fourth gate electrode, the ninth gate electrode, and the eighth gate electrode as masks;
• and
• doping the semiconductor layer in the p-channel TFT with a p-type impurity element while covering the n-channel TFT and the pixel TFT with a resist mask and using the ninth gate electrode as a mask.

A method of manufacturing an electrical device, comprising steps of:

• forming an amorphous semiconductor layer on an insulating surface;
• doping the amorphous semiconductor layer with a catalytic element for promoting crystallization;
• heating the amorphous semiconductor layer doped with the catalytic element and then irradiating the semiconductor layer with a laser to obtain a crystalline semiconductor layer;
• forming a gate insulating film on the crystalline semiconductor layer;
• forming a first conductive film and a second conductive film on the gate insulating film;
• etching the first conductive film and the second conductive film to form a first gate electrode, a second gate electrode, and a third gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the first gate electrode, the second gate electrode, and the third gate electrode;
• etching the first gate electrode, the second gate electrode, and the third gate electrode to form a fourth gate electrode, a fifth gate electrode, and a sixth gate electrode;
• doping the semiconductor layer with an n-type impurity element while using as masks the fourth gate electrode, the fifth gate electrode, and the sixth gate electrode;
• etching the fifth gate electrode of a p-channel TFT and the sixth gate electrode of a pixel TFT to form a seventh gate electrode and an eighth gate electrode, respectively, while covering with a resist mask an n-channel TFT that is formed in a driving circuit;
• etching the seventh gate electrode to form a ninth gate electrode;
• removing the gate insulating film while using the fourth gate electrode, the ninth gate electrode, and the eighth gate electrode as masks;
• and
• doping the semiconductor layer in the p-channel TFT with a p-type impurity element while covering the n-channel TFT and the pixel TFT with a resist mask and using the ninth gate electrode as a mask.