Semiconductor processing methods and structures for determining alignment during semiconductor wafer processing

A semiconductor processing method of determining alignment during semiconductor wafer processing comprising:

• forming a first layer over a substrate;
• forming a first pattern within the first layer, said first pattern defining a four-sided geometric figure;
• forming a second layer over the first layer;
• forming an alignment pattern over the second layer, said alignment pattern overlapping with the first pattern to define an alignment pattern portion which, when viewed from a point over the substrate, is disposed outwardly of the four sides of the first pattern;
• and
• inspecting said patterns and ascertaining from said alignment pattern portion whether a misalignment exists between the patterns and if so, a magnitude of misalignment.

A semiconductor processing method of determining alignment during semiconductor wafer processing comprising:

• forming a first, multi-sided, generally rectilinearly-formed pattern within a layer provided over a substrate;
• forming a masking layer over said layer;
• superimposing in said masking layer, a second, multi-sided, generally rectilinearly-formed pattern over the first pattern, at least one of the sides of the second pattern, when viewed from a point over the substrate, being disposed at an angle which is generally oblique relative to one of the sides of the first pattern;
• and
• inspecting relative positions between the first and second patterns to determine alignment in one direction.

A semiconductor processing method of determining alignment during semiconductor wafer processing comprising:

• forming a first pattern over a semiconductor substrate, said first pattern defining a first geometry defined by a plurality of sides arranged at predetermined angles relative to one another;
• superimposing a second pattern over the first pattern, said second pattern defining a second geometry which is different from the first geometry, said second geometry being defined by a plurality of sides arranged at predetermined angles relative to one another which are different from the predetermined angles at which first pattern sides are arranged;
• providing a series of graduations proximate one of the first and second patterns;
• and
• inspecting relative positions between the first and second patterns to ascertain alignment between the two patterns and responsive to a perceived misalignment between the patterns, inspecting the series of graduations to quantify the misalignment.

A semiconductor alignment method comprising:

• defining a single geometric shape at one substrate elevation;
• defining at least two lines disposed at a different substrate elevation;
• and
• visually inspecting said geometric shape and said two lines for a shift of both of said two lines away from known positions relative to said geometric shape, and translating said shift, if any, into respective quantifiable shift magnitudes associated with a shift in X and Y directions.