Control unit having a main microprocessor and having a processor interface to a bus transceiver unit
AssigneeBayerische Motoren Werke Aktiengesellschaft
InventorsJoachim Froeschl, Josef Krammer, Anton Schedl
Life of this patent
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Abstract
A control unit has a main microprocessor and processor interface to a bus transceiving unit, which has at least one transmit memory, one receive memory and one bus controller. Devices are provided by which the data content of the transmit memory and/or of the receive memory is reset to a defined status after each output and/or reading-in of the data stored in either memory, and before the main microprocessor outputs and/or reads in new data.
Claims10
A control unit comprising:
- a main microprocessor;
- and
- a bus transceiver unit having a processor interface, at least one transmit memory, one receive memory and one bus controller;
- and
- means for resetting a data content of at least one of the transmit memory and the receive memory after each occurrence of an output or reading-in of data stored in the transmit or receive memory to a defined status before the main microprocessor outputs or reads in new data.
A method for operating a control unit having a main microprocessor and a bus transceiver unit with a transmit memory, a receive memory and a bus controller, comprising:
- after each occurrence of an output or read-in of data stored in the transmit memory or the receive memory, resetting a data content of the transmit or receive memory, to a defined status;
- and
- the main microprocessor outputting or reading in new data after said resetting.
Dependencies are inferred from the claim text.