H-bridge motor driving circuit four

An H-bridge motor driving circuit comprising:

• an H-bridge output circuit for driving a motor, said H-bridge output circuit including first and second MOS transistors having sources and drains, either of which are connected to a first terminal of a DC power supply, parasitic diodes existing between the sources and the drains and to which a voltage of the DC power supply is applicable in a reverse direction, and gates for being supplied with control signals to control conduction/non-conduction of the first and second MOS transistors, and third and fourth MOS transistors having sources and drains, either of which are connected to the other of the sources and the drains of said first and second MOS transistors and others of which are connected to a second terminal of the DC power supply, parasitic diodes existing between the sources and the drains and to which the voltage of the DC power supply is applicable in a reverse direction, and gates for being supplied with control signals to control conduction/non-conduction of the third and fourth MOS transistors, said motor being connected between a junction between said first and third MOS transistors and a junction between said second and fourth transistors;
• a triangular wave oscillator for generating a triangular wave signal;
• a PWM comparator for comparing said triangular wave signal with a constant-level signal;
• first and second frequency dividers, each frequency-dividing, by 2, an output signal from said PWM comparator with positive-going edges and negative-going edges, respectively, thereof;
• an AND gate for ANDing an output signal from said first frequency divider and an output signal from said second frequency divider;
• an OR gate for ORing the output signal from said first frequency divider and the output signal from said second frequency divider;
• first and second inverters, each inverting an output signal from said AND gate and an output signal from said OR gate, respectively;
• and
• a control circuit for applying an output signal from said first inverter, an output signal from said second inverter, the output signal from said AND gate, and the output signal from said OR gate to the gates of the first, second, third, and fourth MOS transistors, respectively.