DMA controller in which bus access ratio can be set
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTetsuya Kagemoto
Life of this patent
Estimating the term…
Abstract
A DMA controller includes: a bus availability frequency register setting a ratio of a bus access frequency of DMA transfer to a bus access frequency of another bus master; a DMA request detecting portion detecting a DMA request; a bus availability counter counting the bus access frequency in accordance with the ratio set in the bus availability frequency counter; a bus access request controlling portion controlling the bus access request based on the DMA request detected by the DMA request detecting portion and the counted result of the counter; and a DMA controlling portion controlling execution of DMA transfer. Thus, a band which allows another bus master to use a bus during DMA transfer can be predicted.
Claims18
A direct memory access controller, comprising:
- a register setting a ratio of a bus access frequency of direct memory access transfer to a bus access frequency of another bus master;
- a direct memory access request detecting portion detecting a direct memory access request;
- a counter counting a bus access frequency in accordance with said ratio set in said register;
- a bus access request controlling portion controlling a bus access request based on said direct memory access request detected by said direct memory access request detecting portion and the counted result of said counter;
- and
- a direct memory access controlling portion controlling execution of direct memory access transfer in accordance with a bus access grant.
A direct memory access transfer method, comprising the steps of:
- setting a ratio of a bus access frequency of direct memory access transfer to a bus access frequency of another bus master;
- detecting a direct memory access request;
- counting a bus access frequency in accordance with said set ratio;
- controlling a bus access request based on said detected direct memory access request and said counted result;
- and
- controlling execution of direct memory access transfer in accordance with a bus access grant.
Dependencies are inferred from the claim text.