Automatic circuit generation apparatus and method, and computer program product for executing the method

The automatic circuit generation method comprising:

• inputting circuit information, to be used for performing an automatic logical circuit generation, including a net list only having MT cells made up of high-threshold voltage transistors and low-threshold voltage transistors, and interpreting the circuit information inputted;
• identifying a path having an adequately-larger timing margin than the timing constraint that has been set in advance by performing a static timing analysis for a logical circuit in the net list based on the result of the analysis for the circuit information inputted;
• and
• replacing the MT cells in the path having the adequately-larger timing margin than the timing constraint with high-threshold cells each made up of high-threshold voltage transistors.

An automatic circuit generation method comprising:

• inputting circuit information, to be used for performing an automatic logical circuit generation, including a net list having high-threshold cells made up of only high threshold voltage transistors and MT cells made up of high threshold voltage transistors and low-threshold voltage transistors mixed, and interpreting the circuit information inputted;
• identifying a path whose delay time in larger than a timing constraint that has been set in advance and a path having an adequately-larger timing margin than the timing constrain by performing a static timing analysis for a logical circuit of the net list based on the result of the analysis for the circuit information inputted;
• and
• replacing high-threshold cells in at least a part of the path whose delay time is larger than the timing constraint with MT cells, and replacing the MT cells in the path of the adequately-larger timing margin with the high-threshold cells without any causing the timing violation.

An automatic circuit generation method comprising;

• inputting circuit information, to be used for performing an automatic logical circuit generation, including a net list having MT cells made up of high-threshold voltage transistors and low-threshold voltage transistors mixed, and interpreting the circuit information inputted;
• identifying a path whose delay time is larger than a timing constraint that has been set in advance by performing a static timing analysis for a logical circuit in the net list based on the result of the interpretation for the circuit information inputted;
• and
• replacing the MT cells in the path of the adequately-larger timing margin than the timing constraint with the high-threshold cells without any causing the timing violation.

An automatic circuit generation apparatus comprising;

• an input process section inputting and interpreting circuit information including a net list of cells forming a logical circuit;
• a timing analysis section performing a static timing analysis for the logical circuit, and based on a result of the interpretation obtained by the input process section, identifying a path whose delay time is larger than a timing constraint that has been net in advance, or identifying a path having an adequately-larger timing margin than the timing constraint:
• a cell replacement section replacing a part of or all of high-threshold cells in the path having the larger delay time than the timing constraint with MT cells in which high threshold voltage transistors and low-threshold voltage transistors are mixed, or replacing MT cells in the path having the adequately-larger timing margin;
• an output section outputting an improved net lint in which the high-threshold cells and the MT cells are mixed based on the replacement result obtained by the cell replacement section.

A computer program product including instructions for executing, by a computer system, an automatic circuit generation method comprising:

• inputting circuit information, to be used in an automatic logical circuit generation, including a net list of cells, and interpreting the circuit information inputted;
• identifying a path whose delay time is larger than a timing constraint that has been set in advance, or a path having an adequately-larger timing margin than the timing constraint, by performing a static timing analysis for a logical circuit of the net list based on the result of the analysis for the circuit information inputted;
• and
• replacing high-threshold calls in at least a part of the path having the larger delay time than the timing constraint with MT cells made up of high-threshold voltage transistors and low-threshold voltage transistors, and replacing MT cells in at least a part of the path having the adequately larger timing margin with the high-threshold cells without any causing the timing violation.