Coding apparatus

A coding apparatus comprising:

• a shift register for performing bit shifting and storing one input bit after another;
• a first input register for storing coefficients of terms on respective orders of a first generator polynomial;
• a second input register for storing coefficients of terms on respective orders of a second generator polynomial;
• a first logical operation section;
• and
• a second logical operation section,
• wherein the first logical operation section obtains logical products of the respective bits stored on the shift register and associated bits stored on the first input register so that the earlier a bit was input to the shift register, the higher-order one of the coefficients in the terms of the first polynomial the input bit is associated with;
• derives an exclusive logical sum of the logical products obtained and a bit of an input bit sequence, which bit is currently input to the first logical operation section;
• and then outputs the sum to the shift register, and
• wherein the second logical operation section obtains logical products of the respective bits stored on the shift register and associated bits stored on the second input register and a logical product of each one bit input to the shift register and an associated bit stored on the second input register so that the earlier the bit was input to the shift register, the higher-order one of the coefficients in the terms of the second polynomial the input bit is associated with;
• derives an exclusive logical sum of the logical products obtained;
• and then outputs the sum as one bit of a code sequence.

A coding method comprising the steps of:

• performing bit shifting on an input bit sequence and storing one bit of the input bit sequence after another on a shift register;
• obtaining logical products of the respective bits stored on the shift register and associated bits stored on an input register and a logical product of each one bit input to the shift register and an associated bit stored on the input register so that the earlier a bit of the input bit sequence was input, the higher-order one of coefficients in respective terms of a generator polynomial the input bit is associated with, the coefficients of the polynomial being stored on the input register;
• and
• deriving an exclusive logical sum of the logical products obtained and then outputting the sum as one bit of a code sequence.

A coding method comprising the steps of:

• performing bit shifting and storing one input bit after another on a shift register;
• obtaining logical products of the respective bits stored on the shift register and associated bits stored on a first input register so that the earlier a bit was input to the shift register, the higher-order one of coefficients in respective terms of a first generator polynomial the input bit is associated with, the coefficients of the first generator polynomial being stored on the first input register;
• deriving an exclusive logical sum of the logical products obtained and a bit of an input bit sequence, which bit is currently input to the shift register, and then outputting the sum to the shift register;
• obtaining logical products of the respective bits stored on the shift register and associated bits stored on a second input register and a logical product of each one bit input to the shift register and an associated bit stored on the second input register so that the earlier the bit was input to the shift register, the higher-order one of coefficients in respective terms of a second generator polynomial the input bit is associated with, the coefficients of the second generator polynomial being stored on the second input register;
• and
• deriving an exclusive logical sum of the logical products obtained and then outputting the sum as one bit of a code sequence.