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US 2002/0002693 A1Published application
Error correction structures and methods
AssigneeTexas Instruments Incorporated
InventorsJagadeesh Sankaran, David Hoyle
Life of this patent
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Abstract
A syndrome evaluation with partitioning of a received block of symbols into subsets and interleaved partial syndrome evaluations to overcome multiplier latency. Parallel syndrome evaluations with a parallel multiplier.
Claims5
A method of BCH decoding, comprising:
- (a) partitioning a received block of n symbols into N subsets with N an integer greater than 1;
- (b) evaluating a partial syndrome for each of said N subsets;
- and
- (c) combining said partial syndrome evaluations to form a first syndrome evaluation.
1 more element
A method of syndrome evaluation, comprising:
- (a) providing a Galois multiplier with latency L cycles with L an integer greater than 1 for P parallel multiplications with P a positive integer;
- (b) partitioning a received block of n symbols into N subsets with N an integer at least equal to L;
- (b) evaluating in parallel partial syndromes for each of said N subsets;
- and
- (c) combining said partial syndrome evaluations to form P syndrome evaluations.
2 more elements
A method of syndrome evaluation, comprising:
- (a) providing a Galois multiplier with latency L cycles with L an integer greater than 1 for P parallel multiplications with P a positive integer;
- (b) partitioning a received block of n symbols into MN subsets with N an integer at least equal to L and M a positive integer;
- (b) evaluating in parallel partial syndromes for each of said MN subsets;
- and
- (c) combining said partial syndrome evaluations to form P syndrome evaluations.
2 more elements
Dependencies are inferred from the claim text.