US 2002/0002669 A1 · DATA PROCESSOR

Abstract

A vector point of an exception handler related to TLB miss exception events is obtained by reading a vector base address of a register VBR one time, and by adding a vector offset (H′400) thereto. A vector point of an exception handler related to exception events other than the TLB miss exception events is obtained by adding a vector offset to a value (vector base address) of the register VBR, and an exception code which is an address offset obtained by reading a value of the register EXPEVT or INTEVT one time is added to the vector point that is obtained. Thus, the processing is branched to a required exception handler to execute the exception event processing related to exception events other than the TLB miss exception events.

Claims11

Dependent claims

A single-chip data processor comprising:

a storage circuit (EXPEVT, INTEVT) into which, in response to an exception event, an exception code assigned in advance to it is stored;
and
a central processing unit (CPU) including a program counter (PC), and a control means (CTRL) which, in response to an exception event, writes a predetermined instruction address into said program counter so that a first exception handler assigned to said instruction address may be executed;
wherein
said control means calculates a second instruction address for branching into a second exception handler from the first exception handler by utilizing the exception code written into the storage circuit as an address offset in accordance with the processing specified in said first exception handler, and sets the obtained second instruction address to the program counter.

2 more elements

Dependencies are inferred from the claim text.

Data processor

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Data processor

Life of this patent

Abstract

Claims11