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AssigneeCompaq Information Technologies Group, L.P.
InventorsSompong Paul Olarig, David J. Koenen, Chai S. Heng
Estimating the term…
A memory controller capable of supporting heterogeneous memory configurations enables seamless communications between a bus and memory modules having different characteristics. Thus, owners of computer systems need no longer replace entire memory arrays to take advantage of new memory modules; some memory modules may be upgraded to a new type while other memory modules of an older type remain. The memory controller receives memory requests from multiple processors and bus masters, identifies a memory module and memory access parameters for each request, accesses the memory and returns the resulting data (during a read request) or stores the data (during a write request). In some systems, the memory controller of the present invention is a two-tier memory controller system having a first memory controller coupled to the bus and to the second tier of memory controllers or RAM personality modules that translate between the first memory controller and a particular type of memory module. Typically, between the tiers a protocol is used which is representative of a typical clocked synchronous dynamic random access memory (SDRAM), although another protocol could be used. From the perspective of the processor bus or host bus coupled to the front end of the first memory controller, the entire memory controller system behaves as a single memory controller. From the perspective of memory, the back end of the RAM personality module is seen as a memory controller designed specifically to be configured for that memory type. Consequently, although the front end of the RAM personality module can be standardized across the system, compatible with the back end of the first memory controller, and in most embodiments of the present invention, the back end of the RAM personality module differs among the controller modules in the second tier, according to the variety of the memory modules in the memory system.
A computer system comprising:
A computer system comprising:
In a computer system having at least a first bus, the bus having address, data, and control signals, at least one processor for processing data, for controlling operations of the bus and for performing read and write operations, and a heterogeneous main memory array, having a first memory unit and a second memory unit, the first and second memory units having different access parameters, a memory controller system coupled to the bus, the memory controller system comprising:
In a computer system having at least a first bus, the bus having address, data, and control signals, at least one processor for processing data, for controlling operations of the bus and for performing read and write operations, and a heterogeneous main memory array, having a first memory unit and a second memory unit, the first and second memory units having different access parameters, a memory controller system coupled to the bus, the memory controller system comprising:
In a computer system having a first bus for transferring address, data, and control signals, at least one for processing data, for controlling operations of the first bus and for performing read and write operations, and a memory controller, a heterogeneous memory array, the heterogeneous memory array comprising:
For connection to a computer system having a first bus for transferring address, data, and control signals, at least one for processing data, for controlling operations of the first bus and for performing read and write operations, and a memory controller, a memory card, the memory card comprising:
In a computer system having a first bus for transferring address, data, and control signals, at least one for processing data, for controlling operations of the first bus and for performing read and write operations, a memory controller for selecting memory modules and for transferring address, data, and control signals between the bus and the selected memory module, and a heterogeneous memory array having a plurality of memory modules coupled to the memory controller, a method for exchanging data between the bus and the selected memory module, the method comprising the steps of:
Dependencies are inferred from the claim text.