US 2002/0002653 A1 · Memory system having flexible addressing and method

Abstract

A non-volatile memory system having a memory controller, an array of memory cells and a memory operation manager. The operation manager carries out memory program, read and erase operation upon receipt of program, read and erase instruction from the controller, typically over a system bus. The address block circuitry is provided in the manager which is capable of performing an memory operation on a single address or on multiple addresses depending upon the state of the address block circuitry as determined by the controller. Multiple addresses can be generated based upon a single address provided by the controller so that sectors of the memory can be programmed or read thereby simplifying memory operations and reducing the overhead of the memory controller.

Claims116

Dependent claims

A memory system comprising:

a memory controller configured to issue memory program instructions, memory read instructions and memory erase instructions, with the program instructions comprising program data information and program address information, with the memory read instructions including read address information;
an array of non-volatile memory cells;
a memory operation manager, operably coupled to the memory controller and to the array, said memory operation manager being configured to carry out memory program operations upon receipt of one of the memory program instructions, memory read operations upon receipt of one of the memory read instructions and memory erase operations upon receipt of one of the memory erase instructions, said memory operations manager comprising
a memory address block, configured to control memory addresses used in memory read and memory program operations, with the memory address block containing a memory address derived from the read address information during memory read operations and derived from the program address information during the memory program operations, with the memory address having a most significant address portion and a least significant address portion, with the memory address block being further configured to modify the least significant address portion independent of the program address and read address information;
and
a memory data block configured to control data used in memory program operations.

3 more elements

A memory system comprising:

a memory system bus;
a memory controller configured to issue instructions over the system bus, with the instructions including memory program instructions, memory read instructions and memory erase instructions, and with the program instructions comprising program data information and program address information, with the memory read instructions comprising read address information;
an array of non-volatile memory cells;
a memory operation manager, operably coupled to the system bus and to the array, said memory operation manager being configured to carry out memory program operations upon receipt of one of the memory program instructions on the system bus, memory read operations upon receipt of one of the memory read instructions on the system bus and memory erase operations upon receipt of one of the memory erase instructions on the system bus, said memory operations manager comprising
a memory address block, configured to control memory addresses used in memory program operations, with the memory address block containing a memory address derived from the program address information, with the memory address having a most significant address portion and a least significant address portion, with the memory address block being further configured to modify the least significant address portion independent of the program address information;
and
a memory data block configured to control data used in memory program operations.

4 more elements

A non-volatile memory system comprising:

a system bus:
a first integrated circuit, operably coupled to the system bus and comprising a memory controller configured to issue memory program instructions over the system bus, memory read instructions over the system bus and memory erase instructions over the system bus, with the program instructions comprising program data information and program address information, with the memory read instructions including read address information;
a second integrated circuit which comprises
(a) an array of non-volatile memory cells;
(b) a memory operation manager, operably coupled to the system bus and to the array, said memory operation manager being configured to carry out memory program operations upon receipt of the memory program instructions over the system bus, memory read operations upon receipt of the memory read instructions over the system bus and memory erase operations upon receipt of the memory erase instructions over the system bus, said memory operations manager comprising
(i) a memory address block, configured to control memory addresses used in memory read and memory program operations, with the memory address block containing a memory address derived from the read address information during memory read operations and derived from the program address information during the memory program operations, with the memory address having a most significant address portion and a least significant address portion, with the memory address block being further configured to modify the least significant address portion independent of the program address and read address information;
and
(ii) a memory data block configured to control data used in memory program operations.

5 more elements

A memory device for use in a memory system which includes a memory controller coupled to the memory device by way of a system bus and which is configured to issue memory program instructions over the system bus, memory read instructions over the system bus and memory erase instructions over the system bus, with the program instructions comprising program data information and program address information, with the memory read instructions comprising read address information, with the memory device comprising:

an array of memory cells;
a memory operation manager, operably coupled to the array of memory cells and to the system bus, said memory operation manager being configured to carry out memory program operations upon receipt of the memory program instructions over the system bus, memory read operations upon receipt of the memory read instructions over the system bus and memory erase operations upon receipt of the memory erase instructions over the system bus, said memory operations manager comprising
(a) a memory address block, configured to control memory addresses used in memory read and memory program operations, with the memory address block containing a memory address derived from the read address information during memory read operations and derived from the program address information during the memory program operations, with the memory address having a most significant address portion and a least significant address portion, with the memory address block being further configured to modify the least significant address portion independent of the program address and read address information;
and
(b) a memory data block configured to control data used in memory program operations.

2 more elements

A method of controlling operation of a memory device by way of a system bus, with the memory device comprising an array of memory cells, said method comprising the following steps:

transferring a first read address over the system bus which corresponds to an address of the memory array to be read;
transferring enable/disable information over the system bus;
transferring at least one command of a read command set over the system bus;
reading the array in response to receipt of the read command set by the memory device at an address corresponding to the first read address;
generating a first modified read address at the memory device based upon the first read address and the enable/disable information;
transferring, subsequent to the step of reading the array at the first read address, at least one command of the read command set over the system bus;
reading the array in response to receipt of the at least one command of the read command set at an address corresponding to the first modified read address;
generating a second modified read address based upon the first modified read address;
transferring, subsequent to the step of reading the array at the first read address, at least one command of the read command set over the system bus;
and
reading the array in response to receipt of the at least one command of the read command at an address corresponding to the second modified read address.

8 more elements

A memory device comprising:

an array of non-volatile memory cells;
a system bus interface;
a memory operation manager, operably coupled to the system bus interface and to the array, said memory operation manager being configured to carry out memory program operations on the array in response to receipt of memory program instructions on the system bus interface, to carry out memory read operations on the array in response to receipt of memory read instructions on the system bus interface;
and to carry out memory erase operations on the array in response to receipt of memory erase instructions on the system bus interface, with said memory operation manger comprising
a memory address block, configured to control memory addresses used in the memory read and memory program operations, with the memory address block containing a memory address derived from read address information present in the memory read instructions during the memory read operations and derived from program address information present in the memory program instructions during the memory program operations, with the memory address having a most significant address portion and a least significant address portion, with the memory address block being further configured to modify the least significant address portion independent of the program address information and read address information;
and
a memory data block configured to control data used in memory program operations.

4 more elements

A memory device comprising:

an array of non-volatile memory cells;
a system bus interface;
a memory operation manager, operably coupled to the system bus interface and to the array, said memory operation manager being configured to carry out memory program operations on the array in response to receipt of memory program instructions on the system bus interface, to carry out memory read operations on the array in response to receipt of memory read instructions on the system bus interface;
and to carry out memory erase operations on the array in response to receipt of memory erase instructions on the system bus interface, with said memory operation manager comprising
a memory address block, configured to control memory addresses used in the memory program operations, with the memory address block containing a memory address derived from program address information present in the memory program instructions during the memory program operations, with the memory address having a most significant address portion and a least significant address portion, with the memory address block being further configured to modify the least significant address portion independent of the program address information;
and
a memory data block configured to control data used in memory program operations.

4 more elements

A memory system comprising:

a memory controller configured to issue memory program instructions, memory read instructions and memory erase instructions, with the program instructions comprising program data information and program address information, with the memory read instructions including read address information;
an array of non-volatile memory cells;
a memory operation manager, operably coupled to the memory controller and to the array, said memory operation manager being configured to carry out memory program operations upon receipt of one of the memory program instructions, memory read operations upon receipt of one of the memory read instructions and memory erase operations upon receipt of one of the memory erase instructions, said memory operations manager comprising
a memory address block, configured to control memory addresses used in memory program operations, with the memory address block containing a memory address derived from the program address information, with the memory address having a most significant address portion and a least significant address portion, with the memory address block being further configured to modify the least significant address portion independent of the program address information;
and
a memory data block configured to control data used in memory program operations.

3 more elements

A memory system comprising:

a memory controller configured to issue memory program instructions, memory read instructions and memory erase instructions, with the program instructions comprising program data information and program address information, with the memory read instructions including read address information;
an array of non-volatile memory cells;
a memory operation manager, operably coupled to the memory controller and to the array, said memory operation manager being configured to carry out memory read operations upon receipt of one of the memory read instructions, memory read operations upon receipt of one of the memory read instructions and memory erase operations upon receipt of one of the memory erase instructions, said memory operations manager comprising
a memory address block, configured to control memory addresses used in memory read operations, with the memory address block containing a memory address derived from the read address information, with the memory address having a most significant address portion and a least significant address portion, with the memory address block being further configured to modify the least significant address portion independent of the read address information;
and
a memory data block configured to control data used in memory program operations.

3 more elements

Dependencies are inferred from the claim text.

Memory system having flexible addressing and method

Life of this patent

Memory system having flexible addressing and method

Life of this patent

Abstract

Claims116