US 2002/0002650 A1 · APPARATUS FOR CONTROLLING A MULTIBANK MEMORY DEVICE

Abstract

An apparatus is described for interleaving bank and page access to a multibank memory device, such as an SDRAM or SLDRAM. An address detector detects a pending page access, and the associated data transfer request is then stored in a page hit register. A control timing chain includes a rank register queue with a bank access input, a page write input, and a page read input. Comparator circuitry provides bank address comparisons to avoid bank conflicts and to control the timing of insertion of the page hit register contents into the appropriate page write or page read input. While a pending page access request is stored in the page hit register, other pending bank access operations can be initiated. Consequently, bank and page accesses can be interleaved in substantially contiguous command cycles, and data transfer bandwidth is correspondingly improved.

Claims15

Dependent claims

A computer system, comprising:

a processor;
a memory operable to store data and having a plurality of banks;
and
a memory controller coupling the processor with the memory, the memory controller operable to initiate a first data transfer request directed to a first of the banks, to temporarily store a second data transfer request that is a page hit to the first bank, and to initiate a third data transfer request directed to a second of the banks prior to initiation of the second data transfer request.

1 more element

A memory controller for controlling operations of a memory having a plurality of banks, comprising:

a request queue operable to store a plurality of data transfer requests;
a control state machine coupled with the request queue and operable to receive the data transfer requests at respective times, the control state machine responsively applying a plurality of control signals to the memory to initiate corresponding data transfer operations therewith;
an address detector coupled with the request queue and operable to determine if an address of a first one of the data transfer requests corresponds to an address of a second one of the data transfer requests, the address detector responsively asserting a hit signal;
a hit register coupled with the request queue and with the address detector, the register operable to receive the asserted hit signal and responsively store the second data transfer request;
and
a control timing chain coupled with the request queue, with the control state machine, and with the hit register, the control timing chain operable to assert a timing control signal to enable the control state machine to receive the data transfer requests, the control timing chain enabling the control state machine to receive the first data transfer request at a first time, to receive the second data transfer request stored in the hit register at a second time, and to receive a third one of the data transfer requests at a third time, the third time being after the first time and prior to the second time.

3 more elements

A memory controller for controlling operations of a memory having a plurality of banks, comprising:

a request queue operable to store first and second data transfer requests;
a control state machine coupled with the request queue and operable to receive each of the data transfer requests at respective times, the control state machine responsively applying a plurality of control signals to the memory to initiate corresponding data transfer operations therewith;
an address detector coupled with the request queue and operable to determine if the first and second data transfer requests are directed to a same page, the address detector responsively asserting a page hit signal;
a page hit register coupled with the request queue and with the address detector, the page hit register operable to receive the asserted page hit signal and responsively store the second data transfer request;
and
a control timing chain coupled with the request queue and with the page hit register, the control timing chain including a rank register queue through which data transfer request information propagates, the rank register queue including a bank access input and a page access input, the bank access input coupled with the request queue to receive first information associated with the first data transfer request, and the page access input coupled with the page hit register to receive second information associated with the second data transfer request.

3 more elements

Dependencies are inferred from the claim text.

Apparatus for controlling a multibank memory device

Life of this patent

Apparatus for controlling a multibank memory device

Life of this patent

Abstract

Claims15