System for managing input/output accesses at a bridge/memory controller by redirecting access to a first i/o address to a second i/o address
AssigneeIntel Corporation
InventorAndrew Martwick
Life of this patent
Estimating the term…
Abstract
An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.
Claims27
An apparatus, comprising:
- an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected;
- an interrupt generator, coupled to the I/O address verification unit, that generates an interrupt if the I/O address is protected;
- and
- an interrupt recorder, coupled to the address verification unit, that records a cause of the interrupt.
A computer system, comprising:
- a bus;
- a processor coupled to the bus;
- a bridge/memory controller, coupled to the bus, that includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected, an interrupt generator, coupled to the I/O address verification unit, that generates an interrupt if the I/O address is protected, and an interrupt recorder, coupled to the address verification unit, that records a cause of the interrupt.
A method for managing input/output (I/O) address accesses, comprising:
- determining whether an I/O address is protected;
- generating an interrupt if the I/O address is protected;
- and
- recording a cause of the interrupt.
A method for handling an interrupt, comprising:
- reading a status register in a bridge/memory controller to determine a cause of the interrupt;
- and
- servicing the interrupt according to the cause recorded in the status register by redirecting an input/output (I/O) access to a first I/O address recorded in the status register to a second I/O address.
A method for handling an interrupt, comprising:
- reading a status register in a bridge/memory controller to determine a cause of the interrupt;
- and
- servicing the interrupt according to the cause recorded in the status register by emulating an I/O function having an address recorded in the status register.
A computer-readable medium having stored thereon a sequence of instructions which when executed by a processor causes the processor to perform the steps of:
- determining whether an input/output (I/O) address is protected;
- generating an interrupt if the I/O address is protected;
- and
- recording a cause of the interrupt.
A computer-readable medium having stored thereon sequences of instructions which when executed by a processor causes the processor to perform the steps of:
- reading a status register in a bridge/memory controller to determine a cause of the interrupt;
- and
- servicing the interrupt according to the cause recorded in the status register by redirecting an input/output (I/O) access to a first I/O address recorded in the status register to a second I/O address.
A computer-readable medium having stored thereon sequences of instructions which when executed by a processor causes the processor to perform the steps of:
- reading a status register in a bridge/memory controller to determine a cause of the interrupt;
- and
- servicing the interrupt according to the cause recorded in the status register by emulating an I/O function having an I/O address recorded in the status register.
Dependencies are inferred from the claim text.