Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
AssigneePTS Corporation
InventorsEdwin F. Barry, Nikos P. Pitsianis, Kevin Coopman
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Abstract
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
Claims46
An array processing system comprising:
- a digital signal processor (DSP);
- a direct memory access (DMA) controller;
- a plurality of processing element (PE) local memories;
- a direct memory access bus utilized by the DMA controller to access the plurality of PE local memories;
- a system memory;
- a system control bus (SCB) connected to the DMA controller;
- and
- a system data bus (SDB) connecting the DMA controller and a plurality of devices, wherein the DMA controller transfers data between the plurality of devices on the SDB.
A direct memory access (DMA controller for supporting efficient data transfers concurrent with host processor computation comprising:
- a first transfer controller which can operate as an independent processor or can work together with another transfer controller to carry out data transfers;
- a system control bus (SCB) connected to the transfer controller;
- a system data bus (SDB) connected to the transfer controller;
- the first transfer controller operating as both a bus master and a bus slave on both the SCB and the SDB.
A transfer controller comprising:
- a set of execution units including an instruction control unit (ICU), a system transfer unit (STU), a core transfer unit (CTU), and an event control unit (ECU);
- an inbound data queue (IDQ) comprising a data first in first out buffer;
- an outbound data queue (ODQ) comprising a data first in first out buffer;
- a system data bus (SDB);
- a system control bus (SCB);
- and
- a direct memory access (DMA) bus.
An instruction format for a transfer instruction comprising:
- a base opcode field indicating that an instruction is of transfer type;
- a C/S filled which indicates a type of transfer unit for the instruction, a control transfer unit (CTU) or a system transfer unit (STU), respectively;
- an I/O field which indicates that the instruction is inbound or outbound, respectively;
- an execute (X) field when set indicates a start transfer event should start immediately after loading the instruction, and when not set indicates that the instruction is loaded but transfer is not initiated;
- a data type field indicates the size of each element transferred;
- an address mode field refers to a data access pattern which must be generated by a transfer unit, either the CTU or STU;
- a transfer count field indicates the number of data elements of the size specified by the data type field are to be transferred before an end of transfer occurs;
- and
- an address parameter field which specifies a starting address for the transfer.
A method for multicast addressing to enable parallel distribution of a data element to more than one and up to all processing elements (PEs) in a system simultaneously comprising the steps of:
- specifying an addressing mode in an address mode field of a transfer control instruction (TCI);
- and
- utilizing another parameter in the TCI to specify which PEs are to accept data transfer.
A method for permuting data before the data is sent to processing elements (PE) for inbound transfers or before being sent to system memories for outbound transfers comprising the steps of:
- reordering data within a data element;
- and
- performing other stream oriented operations including masking, data merging or complementing.
A method for performing processing element (PE) packing-gather operations comprising the following steps:
- setting a packing-gather operations type indicator to indicate that each PE drives data onto a different group of data wires to return to a transfer controller ODQ;
- and
- determining the packing-gather operations type indicator to control PE deriving of data.
A method for performing processing element (PE) relative gather-sum operations comprising:
- specifying a summary transfer parameter, N, specifying a number of data elements which are to be summed as they are read from local memories;
- summing the N elements to form a single data element;
- repeating the previous steps;
- and
- transferring a single data element to an ODQ as a sum result for every N elements read from local memories.
A method for performing processing element (PE) relative unpack-distribute operations comprising the steps of:
- setting an unpack-distribute operations type indicator to indicate that each PE LMIU receives data from a different group of data wires to be written to its local memory;
- and
- determining the unpack-distribute operations type indicator to control each PE LMIU's receipt of data.
Dependencies are inferred from the claim text.