Processor with reconfigurable arithmetic data path

A method of floating point mantissa multiplication during two pipeline operations comprising the steps of:

• generating partial product signals from a plurality of arithmetic data signals representing mantissas of numbers to be multiplied;
• adding the partial product signals using a multiple-level adder tree to generate a product signal representing the product of the arithmetic data signals at an output level of the adder tree;
• accumulating in first pipeline registers intermediate level signals output from one level of the adder tree for input to a subsequent level of the adder tree;
• wherein a first pipeline operation comprising generating said partial product signals and accumulating said intermediate level signals in said first pipeline registers is carried out in one clock cycle;
• accumulating in second pipeline registers output signals from a further adder comprising local carry propagate adder cells;
• selectively feeding back to an input of said further adder signals representing a constant or the contents of at least some of said second pipeline registers;
• and supplying said product signal as another input to said further adder;
• wherein said inputs to said further adder are aligned with the precision components of a output signal from said further adder stored by said second pipeline registers;
• and wherein the signal alignment, storage of said output signal from said further adder in said second pipeline registers, and said selective feedback are effected during a single clock cycle subsequent to said one clock cycle.