Low sheet resistance of titanium salicide process

The method of claim a wherein said creating a CMOS device structure is:

• Defining Field Oxide Isolation Regions in the silicon substrate thereby defining the active device region;
• Forming a thin layer of oxide on the surface of the substrate;
• Depositing a layer of polysilicon over said thin layer of oxide;
• Masking and etching said layer of polysilicon thereby including said thin layer of oxide thereby forming a polysilicon gate separated from the substrate by a thin layer of oxide;
• Performing a Lightly Doped Diffusion of the source and drain regions in said substrate;
• Forming oxide sidewalls spacers on the sidewalls of said polysilicon gate thereby including said thin layer of oxide;
• and
• Performing a second implant to set the conductivity of said gate region to the desired level and to complete the conductivity of said source/drain regions.

A method of Titanium salicide formation on the substrate using a silicon injection process comprising the steps of:

• Providing a silicon substrate;
• Creating a CMOS device structure on said substrate;
• Vacuum baking said substrate;
• Performing Pre-Amorphorizing Implantation (PAI) upon said substrate;
• Performing a one step HF dip of said substrate,
• Depositing a layer of titanium over the source/drain regions in the surface of said substrate and the polysilicon gate region;
• Performing a first Rapid Thermal Annealing process of said substrate;
• Performing a selective etching of said substrate thereby forming contact areas for the self-aligned source and drain regions in the surface of said substrate;
• and
• Performing a second Rapid Thermal Annealing process of said substrate thereby forming a thin layer of low sheet resistance titanium over said source and drain regions in said substrate.

A method of Titanium salicide formation on the substrate using a silicon injection process comprising the steps of:

• Providing a silicon substrate;
• Creating a CMOS device structure on said substrate;
• Vacuum baking said substrate;
• Performing a one step HF dip of said substrate;
• Depositing a layer of titanium over the source/drain regions in the surface of said substrate and the polysilicon gate region;
• Performing a first Rapid Thermal Annealing process of said substrate;
• Performing a selective etching of said substrate thereby forming contact areas for the self-aligned source and drain regions in the surface of said substrate;
• and
• Performing a second Rapid Thermal Annealing process of said substrate thereby forming a thin layer of low sheet resistance titanium over said source and drain regions in said substrate.