Random access memory
AssigneeMicron Technology, Inc.
InventorsKirk D. Prall, Robert Kerr, Christopher Murphy, D. Mark Durcan
Life of this patent
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Abstract
A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source/drain regions are formed on the substrate adjacent to opposite sides of the gate electrodes. N-type impurities, preferably phosphorous atoms, are then implanted into the first source/drain region which will serve as the capacitor buried contact.
Claims22
A process for making an integrated circuit device, comprising:
- a. forming a gate insulating layer on a substrate having a first conductivity type and a gate electrode on the gate insulating layer;
- b. forming first and second source/drain regions on the substrate adjacent sides of the gate electrode, each source/drain region having a second conductivity type opposite the first conductivity type, the first source/drain region defining the location of a capacitor buried contact;
- and
- c. implanting a second conductivity type dopant into at least a portion of the first source/drain region.
A process for making an integrated circuit device, comprising:
- a. forming a gate insulating layer on a substrate having a first conductivity type and a gate electrode on the gate insulating layer;
- b. implanting a first conductivity type dopant into the substrate on opposite sides of the gate electrode;
- c. implanting a second conductivity type dopant into portions of the substrate on opposite sides of the gate electrode previously doped to a first conductivity type in step (b) to form first and second source/drain regions, the first source/drain region defining the location of a buried contact;
- and
- d. implanting a second conductivity type dopant into at least a portion of the first source/drain region.
In a process for forming an integrated circuit device, the device comprising a semiconductor substrate having a first conductivity type, a gate insulating layer on the substrate, a gate electrode on the gate insulating layer, and a source/drain region having a second conductivity type in the surface of the substrate adjacent one side of the gate electrode, the process comprising;
- a. implanting a second conductivity type dopant into at least a portion of the source/drain region;
- and
- b. forming a polysilicon conductor in electrical contact with the source/drain region.
A process for making an integrated circuit device, comprising:
- a. forming a gate insulating layer on a substrate having a first conductivity type and a gate electrode on the gate insulating layer;
- b. implanting a first conductivity type dopant into the substrate on opposite sides of the gate electrode;
- c. implanting a second conductivity type dopant into portions of the substrate on opposite sides of the gate electrode previously doped to a first conductivity type in step (b) to form first and second source/drain regions, the first source/drain region defining the location of a buried contact;
- d. forming an insulating layer over the structure previously formed;
- e. patterning and etching the insulating layer to form substantially vertical spacers along opposite sides of the gate electrode and to expose a portion of the first source/drain region;
- and
- f. implanting a second conductivity type dopant into the exposed portion of the first source/drain region.
Dependencies are inferred from the claim text.