Semiconductor memory device for reducing power consumption during refresh

Abstract

A semiconductor memory device that reduces the level of power consumption during a refresh operation includes a controller for generating a refresh signal in response to an auto-refresh signal and a self-refresh signal. The semiconductor memory device further includes a bank counter for generating a bank selection signal and a bank count signal, which are used in selecting a bank in response to the refresh signal, and a bank selector for generating a first and a second bank enable signal that are used to selectively enable each bank in response to the bank selection signal and the bank count signal. Additionally, the semiconductor memory device includes a refresh counter controller for generating a counter active signal in response to the bank selection signal and the refresh signal and a refresh counter for generating a row address signal that is used to access the memory cell in response to the counter active signal.

Dependencies are inferred from the claim text.