Method of making an integrated circuit device having a planar interlevel dielectric layer
OwnerMahjoub Ali Abdelgadir, Alvaro Mauryinventors
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Abstract
A method of making an integrated circuit includes depositing a conductive layer, having conductive lines with gaps therebetween, adjacent a semiconductor substrate. A fluoro-silicate glass (FSG) layer is deposited by high-density plasma chemical vapor deposition (HDP-CVD), over the patterned conductive layer and to fill the gaps between conductive lines. The method further includes chemically mechanically polishing the FSG layer and depositing an undoped oxide layer on the FSG layer. Peaks of the FSG layer which correspond to the widths of the conductive metal lines are reduced by the CMP step. Thus, a subsequent conductive layer is substantially protected from exposure to fluorine from the FSG layer.
Claims29
A method of making an integrated circuit comprising the steps of:
- forming a conductive layer, having conductive lines with gaps therebetween, adjacent a semiconductor substrate;
- depositing a fluoro-silicate glass (FSG) layer, by high-density plasma chemical vapor deposition (HDP-CVD), over the patterned conductive layer and to fill the gaps between conductive lines;
- chemically mechanically polishing the FSG layer;
- and
- depositing an undoped oxide layer on the FSG layer.
A method of making an integrated circuit comprising the steps of:
- forming a metal layer, having metal lines with gaps therebetween, adjacent a semiconductor substrate;
- depositing a fluoro-silicate glass (FSG) layer, by high-density plasma chemical vapor deposition (HDP-CVD), over the patterned metal layer and to fill the gaps between metal lines, the FSG layer having peaks corresponding to the metal lines;
- chemically mechanically polishing the FSG layer to reduce a height of the peaks to a substantially uniform height;
- depositing an undoped oxide layer on the FSG layer;
- and
- chemically mechanically polishing the undoped oxide layer.
A method of making a composite interlevel dielectric for an integrated circuit including metal lines having gaps therebetween, the method comprising the steps of:
- depositing a fluoro-silicate glass (FSG) layer over the metal lines and to fill the gaps between the metal lines, the FSG layer having peaks overlying the metal lines;
- chemically mechanically polishing the FSG layer to reduce a height of the peaks to a substantially uniform height;
- and
- depositing an undoped oxide layer on the FSG layer.
Dependencies are inferred from the claim text.