Acquisition of a spread-spectrum signal using counters

An improvement for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising:

• a shift register for storing a replica or delayed replica of the chip-sequence signal, with said shift register having a plurality of taps corresponding to the plurality of chips, respectively;
• a plurality of comparators, with each comparator having a multiplicity of inputs coupled to a multiplicity of taps, respectively, of the plurality of taps, connected to the plurality of taps, respectively, for comparing a multiplicity of chips of the chip-sequence signal embedded in the spread-spectrum signal, with a multiplicity of chips of the replica of the chip-sequence signal stored in said shift register, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values;
• a plurality of counters, connected to the plurality of comparators, respectively, for up and down counting, from each comparator, a respective multiplicity of compared values, respectively, appearing at an output of a respective comparator of said plurality of comparators, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters;
• and
• selecting means, coupled to said plurality of counters, for selecting a value from the plurality of totals.

An improvement for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising:

• shift-register means for storing a replica or delayed replica of the chip-sequence signal, with said shift-register means having a plurality of taps corresponding to the plurality of chips, respectively;
• comparator means, connected to the plurality of taps, respectively, for comparing the chip-sequence signal embedded in the spread-spectrum signal with the replica of the chip-sequence signal stored in said shift-register means, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values;
• counter means, connected to each output of said comparator means, respectively, for up and down counting, from each output of said comparator means, a respective multiplicity of compared values, respectively, appearing at each output of said comparator means, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters;
• and
• selecting means, coupled to said counter means, for selecting a value from the plurality of totals.

An improvement for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising:

• shift-register means for storing a replica or delayed replica of the chip-sequence signal, with said shift-register having a plurality of taps corresponding to the plurality of chips, respectively;
• a plurality of comparators, with each comparator having a multiplicity of inputs coupled to a multiplicity of taps, respectively, of the plurality of taps, connected to the plurality of taps, respectively, for comparing a multiplicity of chips of the chip-sequence signal embedded in the spread-spectrum signal, with a multiplicity of chips of the replica of the chip-sequence signal stored in said shift register, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values;
• counter means connected to the plurality of comparators, respectively, for up and down counting, from each comparator, a respective multiplicity of compared values, respectively, appearing at an output of a respective comparator of said plurality of comparators, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters;
• and
• selecting means, coupled to said counter means, for selecting a value from the plurality of totals.

A method for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising the steps of:

• storing a replica or delayed replica of the chip-sequence signal in a device having a plurality of taps corresponding to the plurality of chips, respectively;
• comparing the chip-sequence signal embedded in the spread-spectrum signal with the replica of the chip-sequence signal present at the plurality of taps, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values;
• up and down counting, from each output of said device, a respective multiplicity of compared values, respectively, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters;
• and
• selecting a value from the plurality of totals.

An method for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising the steps of:

• cycling, in a device, a replica or delayed replica of the chip-sequence signal, with said device having a plurality of taps corresponding to the plurality of chips, respectively;
• comparing a multiplicity of chips of the chip-sequence signal embedded in the spread-spectrum signal, with a multiplicity of chips of the replica of the chip-sequence signal stored in said device, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values;
• up and down counting a respective multiplicity of compared values, respectively, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters;
• and
• selecting a value from the plurality of totals.

An improvement for acquiring synchronization to a chip-sequence signal having, a plurality of chips, embedded in a spread-spectrum signal, comprising:

• a set of M shift registers, where M is a number of shift registers, with each shift register for storing a replica or delayed replica of the chip-sequence signal, with each shift register having a plurality of taps corresponding to the plurality of chips, respectively;
• a plurality of comparators, connected to the plurality of taps of the set of M shift registers, respectively, for comparing, with a delay of 1/M chip duration per shift register of the set of M shift registers, the chip-sequence signal embedded in the spread-spectrum signal with the replica of the chip-sequence signal stored in said shift register, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values;
• a plurality of counters, connected to the plurality of comparators, respectively, for up and down counting, from each comparator, a respective multiplicity of compared values, respectively, appearing at an output of a respective comparator of said plurality of comparators, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters;
• and
• selecting means, coupled to said plurality of counters, for selecting a value from the plurality of totals.

An improvement for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising:

• a set of M shift registers, with each shift register for storing a replica or delayed replica of the chip-sequence signal, with each shift register having a plurality of taps corresponding to the plurality of chips, respectively;
• a plurality of comparators, with each comparator having a multiplicity of inputs coupled to a multiplicity of taps, respectively, of the plurality of taps, connected to the plurality of taps of the set of M shift registers, respectively, for comparing, with a delay of 1/M chip duration per shift register of the set of M shift registers, a multiplicity of chips of the chip-sequence signal embedded in the spread-spectrum signal, with a multiplicity of chips of the replica of the chip-sequence signal stored in said shift register, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values;
• a plurality of counters, connected to the plurality of comparators, respectively, for up and down counting, from each comparator, a respective multiplicity of compared values, respectively, appearing at an output of a respective comparator of said plurality of comparators, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters;
• and
• selecting means, coupled to said plurality of counters, for selecting a value from the plurality of totals.

An improvement for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising:

• shift-register means for storing a plurality of delayed replicas of the chip-sequence signal, with each replica delayed by 1/M chip duration, with said shift-register means having a plurality of taps corresponding to the plurality of chips, respectively, of the plurality of delayed replicas of the chip-sequence signal;
• comparator means, connected to the plurality of taps, respectively, for multiply comparing, with a delay of 1/M chip duration, the chip-sequence signal embedded in the spread-spectrum signal with the plurality of delayed replicas of the chip-sequence signal stored in said shift-register means, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values;
• counter means, connected to each output of said comparator means, respectively, for up and down counting, from each output of said comparator means, a respective multiplicity of compared values, respectively, appearing at each output of said comparator means, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters;
• and
• selecting means, coupled to said counter means, for selecting a value from the plurality of totals.

An improvement for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising:

• shift-register means for storing a replica or delayed replica of the chip-sequence signal, with said shift-register having a plurality of taps corresponding to the plurality of chips, respectively;
• a plurality of comparators, with each comparator having a multiplicity of inputs coupled to a multiplicity of taps, respectively, of the plurality of taps, connected to the plurality of taps, respectively, for comparing a multiplicity of chips of the chip-sequence signal embedded in the spread-spectrum signal, with a multiplicity of chips of the replica of the chip-sequence signal stored in said shift register, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values;
• counter means connected to the plurality of comparators, respectively, for up and down counting, from each comparator, a respective multiplicity of compared values, respectively, appearing at an output of a respective comparator of said plurality of comparators, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters;
• and
• selecting means, coupled to said counter means, for selecting a value from the plurality of totals.

A method for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising the steps of:

• storing a set of M replicas of the chip-sequence signal in a device having a plurality of taps per replica of the chip-sequence signal, with each plurality of taps corresponding to the plurality of chips, respectively;
• comparing, with a delay of 1/M chip duration per chip-sequence signal, the chip-sequence signal embedded in the spread-spectrum signal with the replica of the chip-sequence signal present at each of the plurality of taps, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values;
• up and down counting, from each output of said device, a respective multiplicity of compared values, respectively, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters;
• and
• selecting a value from the plurality of totals.

An method for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising the steps of:

• cycling, in a device, a set of M replicas of the chip-sequence signal, with said device having a plurality of taps corresponding to the plurality of chips, respectively;
• comparing, with a delay of 1/M chip duration per replica of the chip-sequence signal, a multiplicity of chips of the chip-sequence signal embedded in the spread-spectrum signal, with a multiplicity of chips of the replica of the chip-sequence signal stored in said device, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values;
• up and down counting a respective multiplicity of compared values, respectively, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters;
• and
• selecting a value from the plurality of totals.

An improvement for acquiring synchronization to a chip-sequence signal having, a plurality of chips, embedded in a spread-spectrum signal, comprising:

• a shift register for storing a replica or delayed replica of the chip-sequence signal, with said shift register storing a multiplicity of processing bits per chip of the chip sequence signal, and with said shift register having a plurality of taps corresponding to the plurality of chips, respectively;
• a plurality of comparators, connected to the plurality of taps, respectively, for comparing, using a multiplicity of processing bits comparison, the chip-sequence signal embedded in the spread-spectrum signal with the replica of the chip-sequence signal stored in said shift register, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values with each compared value having a multiplicity of processing bits;
• a plurality of counters, connected to the plurality of comparators, respectively, for up and down counting, from each comparator, using a multiplicity of processing bits, a respective multiplicity of compared values, respectively, appearing at an output of a respective comparator of said plurality of comparators, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters, with each total of the plurality of totals having a multiplicity of processing bits;
• and
• selecting means, coupled to said plurality of counters, for selecting, using a soft decision criteria, a value from the plurality of totals.

An improvement for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising:

• a shift register for storing a replica or delayed replica of the chip-sequence signal, with said shift register storing a multiplicity of processing bits per chip of the chip sequence signal, and with said shift register having a plurality of taps corresponding to the plurality of chips, respectively;
• a plurality of comparators, with each comparator having a multiplicity of inputs coupled to a multiplicity of taps, respectively, of the plurality of taps, connected to the plurality of taps, respectively, for comparing, using a multiplicity of processing bits comparison, a multiplicity of chips of the chip-sequence signal embedded in the spread-spectrum signal, with a multiplicity of chips of the replica of the chip-sequence signal stored in said shift register, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values with each compared value having a multiplicity of processing bits;
• a plurality of counters, connected to the plurality of comparators, respectively, for up and down counting at a rate by numbers one to 2N, where N is a number of processing bits, from each comparator, using a multiplicity of processing bits, a respective multiplicity of compared values, respectively, appearing at an output of a respective comparator of said plurality of comparators, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters, with each total of the plurality of totals having a multiplicity of processing bits;
• and
• selecting means, coupled to said plurality of counters, for selecting, using a soft decision criteria, a value from the plurality of totals.

An improvement for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising:

• shift-register means for storing a replica or delayed replica of the chip-sequence signal, with said shift-register means storing a multiplicity of processing bits per chip of the chip sequence signal, with said shift-register means having a plurality of taps corresponding to the plurality of chips, respectively;
• comparator means, connected to the plurality of taps, respectively, for comparing, using a multiplicity of processing bits comparison, the chip-sequence signal embedded in the spread-spectrum signal with the replica of the chip-sequence signal stored in said shift-register means, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values with each compared value having a multiplicity of processing bits;
• counter means, connected to each output of said comparator means, respectively, for up and down counting, from said comparator means, using a multiplicity of processing bits, a respective multiplicity of compared values, respectively, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters, with each total of the plurality of totals having a multiplicity of processing bits;
• and
• selecting means, coupled to said counter means, for selecting, using a soft decision criteria, a value from the plurality of totals.

An improvement for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising:

• shift-register means for storing a replica or delayed replica of the chip-sequence signal, with said shift-register means storing a multiplicity of processing bits per chip of the chip sequence signal, with said shift-register means having a plurality of taps corresponding to the plurality of chips, respectively;
• a plurality of comparators, with each comparator having a multiplicity of inputs coupled to a multiplicity of taps, respectively, of the plurality of taps, connected to the plurality of taps, respectively, for comparing, using a multiplicity bit comparison, a multiplicity of chips of the chip-sequence signal embedded in the spread-spectrum signal, with a multiplicity of chips of the replica of the chip-sequence signal stored in said shift register, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values with each compared value having a multiplicity of processing bits;
• counter means, connected to each output of said plurality of comparators, for up and down counting, using a multiplicity of processing bits, a respective multiplicity of compared values, respectively, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters, with each total of the plurality of totals having a multiplicity of processing bits;
• and
• selecting means, coupled to said counter means, for selecting, using a soft decision criteria, a value from the plurality of totals.

A method for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising the steps of:

• storing, in a shift register having a plurality of taps, a replica or delayed replica of the chip-sequence signal, with the chip-sequence signal having a multiplicity of processing bits per chip;
• comparing, using a multiply bit comparison, the chip-sequence signal embedded in the spread-spectrum signal with the replica of the chip-sequence signal present at the plurality of taps, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values with each compared value having a multiplicity of processing bits;
• up and down counting, using multiply bit counting, from each output of said device, a respective multiplicity of compared values, respectively, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters, with each total having a multiplicity of processing bits;
• and
• selecting, using a sift decision criteria, a value from the plurality of totals.

An method for acquiring synchronization to a chip-sequence signal, having a plurality of chips, embedded in a spread-spectrum signal, comprising the steps of:

• cycling, in a device, a replica or delayed replica of the chip-sequence signal, with the chip-sequence signal having a multiplicity of processing bits per chip, with said device having a plurality of taps corresponding to the plurality of chips, respectively;
• comparing, using a multiply bit comparison, a multiplicity of chips of the chip-sequence signal embedded in the spread-spectrum signal, with a multiplicity of chips of the replica of the chip-sequence signal stored in said device, thereby generating for the plurality of taps of said device a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values with each compared value having a multiplicity of processing bits;
• up and down counting a respective multiplicity of compared values, respectively, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters, with each total having a multiplicity of processing bits;
• and
• selecting, using a soft decision criteria, a value from the plurality of totals.