Integrated circuit device which outputs data after a latency period transpires

A semiconductor subsystem bus for interconnecting semiconductor devices comprising

• a plurality of semiconductor devices connected in parallel to a bus, at least one of said semiconductor devices being a memory device or a transceiver device which in turn is connected to a memory subsystem,
• said bus including a plurality of bus lines for carrying substantially all address, data and control information needed by said semiconductor devices,
• said control information including semiconductor device-select information,
• said bus containing substantially fewer bus lines than the number of bits in a single address, and
• said bus carrying device-select information without the need for separate device-select lines connected directly to individual semiconductor devices, and
• at least one modifiable register in each of the semi-conductor devices on said bus, said modifiable registers being accessible from said bus, whereby the subsystem can be configured using signals transmitted on said bus.

A bus subsystem comprising

• two semiconductor devices connected in parallel to a bus, wherein one of said semiconductor devices is a master device,
• said master device including a means for initiating bus transactions,
• said bus including a plurality of bus lines for carrying substantially all address, data and control information needed by said devices,
• said control information including device-select information,
• said bus containing substantially fewer lines than the number of bits in a single address, and
• said bus carrying device-select information without the need for separate device-select lines connected directly to individual devices on said bus, whereby said master device initiates bus transactions which transfer information between said semiconductor devices on said bus.

A bus subsystem comprising

• a memory device and a master device connected in parallel on a bus,
• a means for said master device to send a request packet and initiate a bus transaction and
• a means for said master device to keep track of current and pending bus transactions,
• said bus including a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices,
• said bus containing substantially fewer lines than the number of bits in a single address, and
• said bus carrying device-select information without the need for separate device-select lines connected directly to individual devices on said bus, whereby said master device initiates bus transactions which transfer information between devices on said bus and collisions on said bus are avoided because said master device avoids initiating bus transactions which would conflict with current or pending bus transactions.

A bus subsystem comprising

• a plurality of semiconductor devices connected in parallel to a bus,
• said bus including a plurality of bus lines for carrying substantially all address, data and control information needed by said semiconductor devices,
• said control information including device-select information,
• said bus containing substantially fewer lines than the number of bits in a single address,
• said bus carrying said device-select information without the need for separate device-select lines connected directly to individual semiconductor devices,
• said semiconductor devices including a reset means having an input and an output, the output of the reset means of one semiconductor device being connected to the input of the reset means of the next semiconductor device in series.

A bus subsystem comprising

• two semiconductor devices connected in parallel to a bus, one of said semiconductor devices being a master device,
• said bus including a plurality of bus data lines for carrying substantially all address, data and control information needed by said semiconductor devices,
• said control information including device-select information,
• said bus containing substantially fewer of said bus data lines than the number of bits in a single address, and
• said bus carrying device-select information without the need for separate device-select lines connected directly to individual semiconductor devices,
• wherein all of said bus data lines are terminated transmission lines and all of said address, data and control information is carried on said bus data lines as a sequential series of bits in the form of low-voltage-swing signals.

A bus subsystem comprising

• two semiconductor devices connected in parallel to a bus having a first and a second end, said bus including a bus clock line, said bus clock line having first and second ends corresponding to said first and second ends of said bus, respectively,
• a clock generator connected to said first end of said bus clock line to generate early bus clock signals with a normal rise time, and
• signal return means at said second end of said bus clock line to return said early bus clock signals to said first end of said bus as corresponding late bus clock signals,
• whereby each of said early bus clock signals will propagate from said clock generator along said clock line starting from said first end to said second end of said bus and then return at a later time to said first end of said bus as a corresponding late bus clock signal, whereby each semiconductor device on said bus can detect said early bus clock signals and said corresponding late bus clock signals.

A DRAM device designed to be connected to an external bus having a plurality of bus lines for carrying substantially all address, data and control information needed by said DRAM device as a sequential series of bits, said control information including device-select information, said external bus containing substantially fewer said bus lines than the number of bits in a single address, and said bus carrying device-select information without the need for separate device-select lines connected directly to said DRAM device, said DRAM device comprising

• an array of memory cells connected in rows and columns, each of said memory cells adapted to store one of said bits,
• a row address selection means for selecting one of said rows,
• a column sense amp connected to each of said columns, each of said column sense amps adapted to latch one of said bits as a binary logical value or to precharge to a selected state,
• a column decoding means connected to each of said column sense amps for selecting a plurality of said column sense amps for inputting one of said bits to or outputting one of said bits from said memory cells,
• an internal I/O bus having a plurality of internal I/O lines wherein each of said internal I/O lines is connected to a plurality of said column sense amps, and
• a plurality of bus connection means designed to connect said internal I/O lines to said external bus,
• whereby a selected bit of said sequential series of bits can be transferred from said external bus to a selected one of said memory cells or said bit contained in a selected one of said memory cells can be transferred to said external bus.

A package containing

• a semiconductor die having a side, circuitry and a plurality of connecting areas positioned along or near said side, spaced at a selected pitch and connected to said circuitry,
• said package comprising a plurality of bus connecting means for connecting to a plurality of external bus lines, each of said external bus lines corresponding to one of said connecting areas, each of said bus connecting means being
• positioned on a first side of said package,
• connected to one said external bus line and to
• said corresponding connecting area on said
• semiconductor die, and
• spaced at a pitch substantially identical to said selected pitch of said connecting areas,
• whereby each of said external bus lines can be connected to said corresponding connecting area on said semiconductor die by bus connection means positioned along a single side of said package.

A semiconductor device capable of use in an architecture for a semiconductor system bus including a plurality of semiconductor devices connected in parallel to a bus wherein said system bus includes a plurality of bus lines for carrying substantially all address, data, control and device-select information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said system bus, and has substantially fewer bus lines than the number of bits in a single address, and carries device-select information for said semiconductor device without the need for a separate device-select line connected directly to said individual semiconductor device, said semiconductor device comprising

• connection means adapted to connect said semiconductor device to said system bus,
• an internal input/output bus within said semiconductor device having more lines than said system bus,
• a means for multiplexing the lines of said internal bus to the lines of said system bus, whereby said system bus can run at a higher speed than said internal bus, and
• at least one modifiable identification register accessible to said system bus through said connection means, whereby data may be transmitted to said register via said system bus and which enables said device thereafter to be uniquely identified.

A semiconductor device capable of use in an architecture for a semiconductor-system bus including a plurality of semiconductor devices connected in parallel to a bus wherein said system bus includes a plurality of bus lines for carrying substantially all address, data, control and device-select information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said system bus, and has substantially fewer bus lines than the number of bits in a single address, and carries device-select information for said semiconductor device without the need for a separate device-select line connected directly to said individual semiconductor device, said semiconductor device comprising

• connection means adapted to connect said semiconductor device to said system bus,
• an internal input/output bus within said semiconductor device having more lines than said system bus,
• a means for multiplexing the lines of said internal bus to the lines of said system bus, whereby said system bus can run at a higher speed than said internal bus, and
• at least one modifiable register to hold device address information, said modifiable register accessible to said system bus through said connection means, whereby data may be transmitted to said register via said system bus which enables said device thereafter to respond to a predetermined range of addresses.

A semiconductor device capable of use in an architecture for a semiconductor system bus including a plurality of semiconductor devices connected in parallel to a bus wherein said system bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said system bus, and has substantially fewer bus lines than the number of bits in a single address, said semiconductor device comprising

• connection means adapted to connect said semiconductor device to said system bus,
• an internal input/output bus within said semiconductor device having more lines than said system bus,
• a means for multiplexing the lines of said internal bus to the lines of said system bus, whereby said system bus can run at a higher speed than said internal bus, and
• at least one modifiable access-time register accessible to said system bus through said connection means, whereby data may be transmitted to said register via said system bus which establishes a predetermined amount of time that said semiconductor device thereafter must wait before using said system bus in response to a request.

A semiconductor device capable of use in a semiconductor bus architecture including a plurality of semiconductor devices connected in parallel to a bus wherein said bus includes a plurality of bus lines for carrying substantially all address, data, control and device-select information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said bus, and has substantially fewer bus lines than the number of bits in a single address, and carries device-select information for said semiconductor device without the need for a separate device-select line connected directly to said individual semiconductor device, wherein said address, data, control and device-select information is carried over said bus in the form of request packets and bus transactions, said semiconductor device comprising

• connection means adapted to connect said semiconductor device to said bus,
• a means to receive said request packets over said bus,
• a means to decode information in said request packets, and
• a means to respond to said information in said request packets.