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US 2002/0001241 A1Published application
Redundancy memory circuit
AssigneeSanyo Electric Co., Ltd.
InventorKazuo Hotaka
Life of this patent
Estimating the term…
Abstract
A memory mat including EEPROM memory has a redundancy memory area for replacing a defective memory area occurring in a main memory area. The most feature of the invention is that a redundancy address memory area for storing address data of the defective memory area is provided in a part of an inforow memory area within the memory mat. The inforow memory area is constructed accessibly only at the time of a test mode.
Claims5
A redundancy memory circuit comprising:
- a main memory area including nonvolatile memories capable of electrically writing and reading, and the main memory area is provided in a memory mat;
- a writing unit for writing redundancy address data corresponding to a defective memory area occurring in the main memory area into a redundancy address memory area provided within the same memory mat as the main memory area;
- and
- a reading unit for reading the redundancy address data according to a trigger signal;
- wherein the defective memory area is repaired on the basis of the redundancy address data read from the redundancy address memory area.
2 more elements
A redundancy memory circuit comprising:
- a main memory area including nonvolatile memories capable of electrically writing and reading, and the main memory area is provided in a memory mat;
- a redundancy address memory area which is provided within the same memory mat as the main memory area and stores redundancy address data corresponding to a defective memory area occurring in the main memory area;
- a redundancy memory area which is provided within the same memory mat as the main memory area and replaces the defective memory area;
- a redundancy control circuit for outputting a control signal for reading the redundancy address data stored in the redundancy address area according to a trigger signal;
- an address comparison circuit for comparing the redundancy address data read according to the control signal with input address data inputted for accessing the main memory;
- and
- an address control circuit for switching the input address data to address data corresponding to the redundancy address memory area when the redundancy address data matches with the input address data.
4 more elements
Dependencies are inferred from the claim text.