Semiconductor integrated circuit and method for controlling activation thereof
AssigneeFujitsu Limited
InventorsKaoru Mori, Masato Matsumiya
Life of this patent
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Abstract
To supply a ground potential Vss to a starter signal level shifter and a fuse information latch circuit on the basis of a fuse starter signal of which low level is shifted from the ground potential Vss to a negative voltage Vnn by the starter signal level shifter until the fuse information is latched to the fuse information latch circuit. After the foregoing fuse information is latched, a finally attained potential is supplied to the starter signal level shifter and the fuse information latch circuit. Therefore, it is possible to latch without shifting the low level, so that it becomes possible to easily shift the low level from the ground potential Vss to the negative voltage Vnn after latching.
Claims17
A semiconductor integrated circuit comprising:
- a latch circuit for latching therein predetermined information in an activation operation after said integrated circuit is powered on;
- and
- a voltage generation circuit having an input signal rising up together with a power supply voltage supplied after said integrated circuit is powered on, and becoming a low level when said power supply voltage reaches a predetermined potential, said voltage generation circuit not performing a voltage generation operation before said predetermined information is latched by said latch circuit, and performing said voltage generation operation after said predetermined information is latched by said latch circuit, on the basis of said input signal or its complementary signal.
A semiconductor integrated circuit comprising:
- a latch circuit for latching therein predetermined information in an activation operation after said integrated circuit is powered on;
- and
- a voltage generation circuit having an input signal having a low level shifted from a first potential to a second potential not more than said first potential, said voltage generation circuit generating, as said second potential, a voltage higher than a finally attained potential before said predetermined information is latched by said latch circuit, and generating said finally attained potential as said second potential after said predetermined information is latched by said latch circuit, on the basis of said input signal.
A method for controlling activation of a semiconductor integrated circuit including a latch circuit for latching predetermined information in an activation operation, said latch circuit having a low level after said activation operation as a finally attained potential, said method comprising:
- supplying a potential not more than a ground potential and higher than said finally attained potential, to said latch circuit as a negative potential, shifting a low level of an input signal from said ground potential to said negative potential, and outputting it, before said predetermined information is latched to said latch circuit;
- and
- supplying said finally attained potential as said negative potential after said predetermined information is latched to said latch circuit on the basis of the output signal.
Dependencies are inferred from the claim text.