Memory circuit with dynamic redundancy
OwnerRichard Ferrantinventor
Life of this patent
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Abstract
The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.
Claims7
An integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and means for reversibly inhibiting the operation of a defective element and for maintaining the circuit operation by using the redundancy element.
Dependencies are inferred from the claim text.