Flash memory cell for high efficiency programming
AssigneeMicron Technology, Inc.
InventorsAndrei Mihnea, Paul J. Rudeck, Chun Chen
Life of this patent
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Abstract
A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.
Claims25
A flash memory cell comprising:
- a control gate, a drain region, a source region, and a channel region formed in a common substrate, the flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and about six volts across a shallow deep-depletion region created near the drain region as a result of a first voltage applied to the control gate, a second voltage applied to the drain region, and a third voltage applied to the source region.
A flash memory cell comprising:
- a control gate, a drain, a source, and a floating gate formed in a common substrate, the flash memory cell is capable of being programmed by applying a first positive voltage to the control gate, applying a second positive voltage to the drain, and applying a third positive voltage to the source, and ramping the first positive voltage at a rate proportional to the injection current to the floating gate.
A flash memory cell comprising:
- a substrate doped with arsenic, boron, and phosphorous;
- and
- a flash memory cell fabricated in connection with the substrate, the flash memory cell having a control gate, a drain, a source, a floating gate, a channel, and an injection current during a programming operation, the flash memory cell is capable of being programmed by applying a first positive voltage to the control gate, applying a second positive voltage to the drain, and applying a third positive voltage to the source, the second positive voltage being greater than the third positive voltage, and the first positive voltage being ramped at a rate proportional to the injection current.
A flash memory cell comprising:
- a source region comprising an arsenic region abutting a heavily doped boron region;
- a drain region comprising an arsenic region abutting a phosphorous region and a lightly doped boron region;
- a channel region doped with boron, the channel region is located between the drain region and the source region;
- and
- a gate dielectric, a floating gate, and a control gate located above the channel region.
A processing system comprising:
- a processor;
- and
- a flash memory cell coupled to the processor and the flash memory cell capable of being programmed with a channel current of about zero.
A method of programming a flash memory cell comprising:
- applying a voltage between 1 volt and 2.5 volts on a source line;
- and
- generating a voltage of more than about four volts across a depletion region in the channel.
A method of programming a flash memory cell having a control gate, a drain, and a source, the method comprising:
- applying a first positive voltage to the control gate;
- applying a second positive voltage to the drain, the first positive voltage being greater than the second positive voltage;
- and
- applying a third positive voltage to the source to suppress the flow of any channel current, the second positive voltage being greater than the third positive voltage.
A method of programming a flash memory cell having a control gate, a drain, and a source, the method comprising:
- applying a voltage of approximately six volts to the control gate;
- applying a voltage of approximately four volts to the drain;
- and
- applying a voltage of approximately two volts to the source.
A method of programming a flash memory cell having a control gate, a drain, and a source, the method comprising:
- applying a voltage of approximately four volts to the drain;
- applying a ramp voltage signal to the control gate, the ramp voltage signal is capable of ramping between about seven and one-half volts and about ten and a half volts at a rate proportional to an injection current;
- and
- applying a voltage of about two volts to the source.
A method of erasing a flash memory cell comprising:
- applying a negative voltage to a gate region;
- and
- applying a positive voltage to a drain region.
Dependencies are inferred from the claim text.